LAN9116 datasheet(94/109 Pages) MICROCHIP

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LAN9116

DS00002268A-page 94

 2005-2016 Microchip Technology Inc.

6.4

RX Data FIFO Direct PIO Reads

In this mode the upper address inputs are not decoded, and any read of the LAN9116 will read the RX Data FIFO. This

mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the

FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address

when accessing the LAN9116. Timing is identical to a PIO read, and the FIFO_SEL signal has the same timing charac-

teristics as the address lines.

Timing for 16-bit and 32-bit Direct PIO Read cycles is identical with the exception that D[31:16] is not driven during a

16-bit read. Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.

FIGURE 6-3:

RX DATA FIFO DIRECT PIO READ CYCLE TIMING

Note:

The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.

TABLE 6-5:

RX DATA FIFO DIRECT PIO READ TIMING

Symbol

Description

MIN

TYP

MAX

Units

tcycle

Read Cycle Time

165

tcsl

nCS, nRD Assertion Time

tcsh

nCS, nRD Deassertion Time

tcsdv

nCS, nRD Valid to Data Valid

tasu

Address, FIFO_SEL Setup to nCS, nRD Valid

tah

Address, FIFO_SEL Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

tdoh

Data Output Hold Time

Note:

An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends

when either or both nCS and nRD are de-asserted. They may be asserted and de-asserted in any order.

Data Bus

nCS, nRD

FIFO_SEL

A[2:1]

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