LAN9116 datasheet(63/109 Pages) MICROCHIP

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DS00002268A-page 63

LAN9116

In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K bytes of TX, and 128

bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by the host.

As space in the TX MIL (Mac Interface Layer) FIFO frees, data is moved into it from the TX data FIFO. Depending on

the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames. This is in addition to any TX data

that may be queued in the TX data FIFO.

Conversely, as data is received by the LAN9116, it is moved from the MAC to the RX MIL FIFO, and then into the RX

data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX MIL FIFO. If the RX MIL FIFO fills up

and overruns, subsequent RX frames will be lost until room is made in the RX data FIFO. For each frame of data that

is lost, the RX Dropped Frames Counter (RX_DROP) is incremented.

RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs operate independent of the TX

adatand RX data and status FIFOs. FIFO levels set for the RX and TX data and Status FIFOs do not take into consid-

eration the MIL FIFOs.

5.3.10

RX_DP_CTRL—RECEIVE DATAPATH CONTROL REGISTER

This register is used to discard unwanted receive frames.

TABLE 5-3:

VALID TX/RX FIFO ALLOCATIONS

TX_FIF_SZ

TX Data FIFO Size

(Bytes)

TX Status FIFO Size

(Bytes)

RX Data FIFO Size

(Bytes)

RX Status FIFO Size

(Bytes)

1536

512

13440

896

2560

512

12480

832

3584

512

11520

768

4608

512

10560

704

5632

512

9600

640

6656

512

8640

576

7680

512

7680

512

8704

512

6720

448

9728

512

5760

384

10752

512

4800

320

11776

512

3840

256

12800

512

2880

192

13824

512

1920

128

Offset:

78h

Size:

32 bits

Bits

Description

Type

Default

RX Data FIFO Fast Forward (RX_FFWD): Writing a ‘1’ to this bit causes

the RX data FIFO to fast-forward to the start of the next frame. This bit will

remain high until the RX data FIFO fast-forward operation has completed.

No reads should be issued to the RX data FIFO while this bit is high.

Note:

Please refer to section “Receive Data FIFO Fast Forward” on

page 43 for detailed information regarding the use of RX_FFWD.

R/W

30-0

Reserved

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