©2002-2016

DS20005022C

04/16

16

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39SF010A / SST39SF020A / SST39SF040

Data Sheet

Figure 9: Toggle Bit Timing Diagram

Figure 10:WE# Controlled Sector-Erase Timing Diagram

1147 F07.1

WE#

OE#

CE#

TWO READ CYCLES

WITH SAME OUTPUTS

Note

Note: Toggled bit output is always high first.

1147 F08.1

WE#

SW0

SW1

SW2

SW3

SW4

SW5

5555

2AAA

2AAA

5555

5555

55

30

55

AA

80

AA

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable

as long as minimum timings are met. (See Table 10)

Toggled bit output is always high first.