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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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WM8281ECS/R Datenblatt(PDF) 271 Page - Cirrus Logic |
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WM8281ECS/R Datenblatt(HTML) 271 Page - Cirrus Logic |
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271 / 392 page  WM8281 Rev 4.0 271 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3:0 ASYNC_CLK_SR C [3:0] 0101 ASYNCCLK Source 0000 = MCLK1 0001 = MCLK2 0010 = Reserved 0011 = Reserved 0100 = FLL1 0101 = FLL2 0111 = Reserved 1000 = AIF1BCLK 1001 = AIF2BCLK 1010 = AIF3BCLK 1011 to 1111 = Reserved All other codes are Reserved R275 (0113h) Async sample rate 1 4:0 ASYNC_SAMPL E_RATE_1 [4:0] 10001 ASYNC Sample Rate 1 Select 00h = None 01h = 12kHz 02h = 24kHz 03h = 48kHz 04h = 96kHz 05h = 192kHz 09h = 11.025kHz 0Ah = 22.05kHz 0Bh = 44.1kHz 0Ch = 88.2kHz 0Dh = 176.4kHz 10h = 4kHz 11h = 8kHz 12h = 16kHz 13h = 32kHz All other codes are Reserved R276 (0114h) Async sample rate 2 4:0 ASYNC_SAMPL E_RATE_2 [4:0] 10001 ASYNC Sample Rate 2 Select Register coding is same as ASYNC_SAMPLE_RATE_1. R283 (011Bh) Async sample rate 1 status 4:0 ASYNC_SAMPL E_RATE_1_STS [4:0] 00000 ASYNC Sample Rate 1 Status (Read only) Register coding is same as ASYNC_SAMPLE_RATE_1. R284 (011Ch) Async sample rate 2 status 4:0 ASYNC_SAMPL E_RATE_2_STS [4:0] 00000 ASYNC Sample Rate 2 Status (Read only) Register coding is same as ASYNC_SAMPLE_RATE_1. R329 (0149h) Output system clock 15 OPCLK_ENA 0 OPCLK Enable 0 = Disabled 1 = Enabled 7:3 OPCLK_DIV [4:0] 00h OPCLK Divider 00h = Divide by 1 01h = Divide by 1 02h = Divide by 2 03h = Divide by 3 … 1Fh = Divide by 31 |
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