WM8281ECSSLASHR datasheet(269/392 Pages) CIRRUS

269 / 392 page

WM8281

Rev 4.0

269

The WM8281 clocking control registers are described in Table 101.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R256

(0100h)

Clock 32k

CLK_32K_ENA

32kHz Clock Enable

0 = Disabled

1 = Enabled

1:0

CLK_32K_SRC

[1:0]

32kHz Clock Source

00 = MCLK1 (direct)

01 = MCLK2 (direct)

10 = SYSCLK (automatically divided)

11 = Reserved

R257

(0101h)

System

Clock 1

SYSCLK_FRAC

SYSCLK Frequency

0 = SYSCLK is a multiple of 6.144MHz

1 = SYSCLK is a multiple of 5.6448MHz

10:8

SYSCLK_FREQ

[2:0]

101

SYSCLK Frequency

000 = 6.144MHz (5.6448MHz)

001 = 12.288MHz (11.2896MHz)

010 = 24.576MHz (22.5792MHz)

011 = 49.152MHz (45.1584MHz)

100 = 73.728MHz (67.7376MHz)

101 = 98.304MHz (90.3168MHz)

110 = 147.456MHz (135.4752MHz)

111 = Reserved

The frequencies in brackets apply for

44.1kHz-related sample rates only (ie.

SAMPLE_RATE_n = 01XXX).

SYSCLK_ENA

SYSCLK Control

0 = Disabled

1 = Enabled

SYSCLK should only be enabled after the

applicable clock source has been

configured and enabled.

Set this bit to 0 when reconfiguring the

clock sources.

3:0

SYSCLK_SRC

[3:0]

0100

SYSCLK Source

0000 = MCLK1

0001 = MCLK2

0100 = FLL1

0101 = FLL2

1000 = AIF1BCLK

1001 = AIF2BCLK

1010 = AIF3BCLK

All other codes are Reserved

WM8281ECS/R Datenblatt(PDF) 269 Page - Cirrus Logic

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