WM8281ECSSLASHR datasheet(302/392 Pages) CIRRUS

302 / 392 page

WM8281

302

Rev 4.0

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R12288

(3000h)

WSEQ

Sequence 1

15:13

WSEQ_DATA_

WIDTH0 [2:0]

000

Width of the data block written in this

sequence step.

000 = 1 bit

001 = 2 bits

010 = 3 bits

011 = 4 bits

100 = 5 bits

101 = 6 bits

110 = 7 bits

111 = 8 bits

12:0

WSEQ_ADDR0

[12:0]

0000h

Control Register Address to be

written to in this sequence step.

R12289

(3001h)

WSEQ

Sequence 2

15:12

WSEQ_DELAY0

[3:0]

0000

Time delay after executing this step.

00h = 3.3us

01h to 0Eh = 61.44us x

((2^WSEQ_DELAY)-1)

0Fh = End of sequence marker

11:8

WSEQ_DATA_S

TART0 [3:0]

0000

Bit position of the LSB of the data

block written in this sequence step.

0000 = Bit 0

…

1111 = Bit 15

7:0

WSEQ_DATA0

[7:0]

00h

Data to be written in this sequence

step. When the data width is less

than 8 bits, then one or more of the

MSBs of WSEQ_DATAn are ignored.

It is recommended that unused bits

be set to 0.

Table 122 Write Sequencer Control - Programming a Sequence

SEQUENCER MEMORY DEFINITION

The Write Sequencer memory defines up to 510 write operations; these are indexed as 0 to 509 in the

sequencer memory map.

Following Power-On Reset (POR), the sequence memory will contain the Boot Sequence, and the

OUT1, OUT2, OUT3, OUT4 signal path enable/disable sequences. The remainder of the sequence

memory will be undefined on power-up.

See the “Applications Information” section for a summary of

the WM8281 memory reset conditions.

User-defined sequences can be programmed after power-up. Note that all control sequences are

maintained in the sequencer memory through Hardware Reset, Software Reset and in Sleep mode.

The default control sequences can be overwritten in the sequencer memory, if required. Note that the

headphone and earpiece output path enable registers (HPnx_ENA, SPKOUTx_ENA) will always

trigger the Write Sequencer (at the pre-determined start index addresses).

Wri

ting ‘1’ to the WSEQ_LOAD_MEM bit will clear the sequencer memory to the POR state.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R24 (0018h)

Write

Sequencer

Ctrl 2

WSEQ_LOAD_

MEM

Writing a 1 to this bit resets the

sequencer memory to the POR state.

Table 123 Write Sequencer Control - Load Memory Control

User-defined sequences must be assigned space within the Write Sequencer memory. The start

index for the user-defined sequences is configured using the registers described in Table 117 and

Table 118.

WM8281ECS/R Datenblatt(PDF) 302 Page - Cirrus Logic

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