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WM8281ECS/R Datenblatt(PDF) 298 Page - Cirrus Logic

Teilenummer WM8281ECS/R
Bauteilbeschribung  Low Power Audio System with Ambient Noise Cancellation and Echo Cancellation
PDF  392 Pages
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Hersteller  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8281ECS/R Datenblatt(HTML) 298 Page - Cirrus Logic

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WM8281
298
Rev 4.0
JACK DETECT, GPIO, MICDET CLAMP, AND WAKE-UP SEQUENCES
The WM8281 supports external accessory detection and GPIO functions. The JD1 signal (associated
with external accessory detection) and the GP5 signal (associated with the GPIO5 pin) can be used to
trigger the Control Write Sequencer.
The JD1 signal is configured using the register bits described in Table 75. The GP5 signal is derived
from the GPIO5 pin, which is configured using the register bits described in Table 86.
The MICDET Clamp is controlled by the JD1 and/or GP5 signals, as described in Table 76. The
MICDET Clamp status can also be used to trigger the Control Write Sequencer.
A Control Write Sequence can be associated with a rising edge and/or a falling edge of the JD1, GP5
or MICDET Clamp. This is configured using the register bits described in Table 85.
If one of the selected logic conditions is detected, the Control Write Sequencer will be triggered. The
applicable start index location within the sequencer memory is separately configurable for each logic
condition.
The WSEQ_GP5_RISE_INDEX register defines the sequencer start index corresponding to a GP5
Rising Edge event. Equivalent start index values are defined for the other logic conditions, as
described in Table 118.
Note that a sequencer start index of 1FFh will cause the respective sequence to be aborted.
The JD1, GP5 and MICDET Clamp control sequences are undefined following Power-On Reset
(POR), but can be user-programmed after power-up. Note that all control sequences are maintained
in the sequencer memory through Hardware Reset, Software Reset and in Sleep mode.
See “Low Power Sleep Configuration” for further details of the JD1, GP5 and MICDET Clamp status
signals. See also “General Purpose Input / Output” for details of the GPIO5 pin.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R102
(0066h)
Always On
Triggers
Sequence
Select 1
8:0
WSEQ_MICD_CL
AMP_RISE_INDE
X [8:0]
1FFh
MICDET Clamp (Rising) Write Sequence
start index
This field contains the index location in
the sequencer memory of the first
command in the sequence associated
with MICDET Clamp (Rising) detection.
Valid from 0 to 509 (1FDh)
R103
(0067h)
Always On
Triggers
Sequence
Select 2
8:0
WSEQ_MICD_CL
AMP_FALL_INDE
X [8:0]
1FFh
MICDET Clamp (Falling) Write Sequence
start index
This field contains the index location in
the sequencer memory of the first
command in the sequence associated
with MICDET Clamp (Falling) detection.
Valid from 0 to 509 (1FDh)
R104
(0068h)
Always On
Triggers
Sequence
Select 3
8:0
WSEQ_GP5_RIS
E_INDEX [8:0]
1FFh
GP5 (Rising) Write Sequence start index
This field contains the index location in
the sequencer memory of the first
command in the sequence associated
with GP5 (Rising) detection.
Valid from 0 to 509 (1FDh)
R105
(0069h)
Always On
Triggers
Sequence
Select 4
8:0
WSEQ_GP5_FAL
L_INDEX [8:0]
1FFh
GP5 (Falling) Write Sequence start index
This field contains the index location in
the sequencer memory of the first
command in the sequence associated
with GP5 (Falling) detection.
Valid from 0 to 509 (1FDh)
R106
(006Ah)
Always On
Triggers
Sequence
Select 5
8:0
WSEQ_JD1_RIS
E_INDEX [8:0]
1FFh
JD1 (Rising) Write Sequence start index
This field contains the index location in
the sequencer memory of the first
command in the sequence associated
with JD1 (Rising) detection.
Valid from 0 to 509 (1FDh)



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