WM8281ECSSLASHR datasheet(299/392 Pages) CIRRUS

299 / 392 page

WM8281

Rev 4.0

299

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R107

(006Bh)

Always On

Triggers

Sequence

Select 6

8:0

WSEQ_JD1_FAL

L_INDEX [8:0]

1FFh

JD1 (Falling) Write Sequence start index

This field contains the index location in

the sequencer memory of the first

command in the sequence associated

with JD1 (Falling) detection.

Valid from 0 to 509 (1FDh)

Table 118 Write Sequencer Control - JD1, GP5 and MICDET Clamp

A valid clock (SYSCLK) must be enabled whenever a Control Write Sequence is scheduled.

If the JD1, GP5 or MICDET Clamp trigger status bits are associated with the Control Write Sequencer

(using the register bits in Table 85) and also configured as Wake-Up events (using the register bits in

Table 84), then the Boot Sequence must be programmed to configure and enable SYSCLK. (Note

that the default SYSCLK frequency must be used in this case.)

The Boot Sequence (see below) is scheduled as part of the Wake-Up transition, and provides the

capability to configure SYSCLK (and other register settings) prior to the Control Write Sequencer

being triggered.

Note that, if the Control Write Sequencer is triggered during normal operation, then SYSCLK will

typically be already available, and no additional requirements will apply.

DRC SIGNAL DETECT SEQUENCES

The Dynamic Range Control (DRC) function within the WM8281 Digital Core provides a configurable

signal detect function. This allows the signal level at the DRC input to be monitored and used to

trigger other events.

The DRC Signal Detect functions are enabled and configured using the register fields described in

Table 15 and Table 16 for DRC1 and DRC2 respectively.

A Control Write Sequence can be associated with a rising edge and/or a falling edge of the DRC1

Signal Detect output. This is enabled using the DRC1_WSEQ_SIG_DET_ENA register bit.

Note that signal detection is supported on DRC1 and DRC2, but the triggering of the Control Write

Sequencer is available on DRC1 only.

When the DRC Signal Detect sequence is enabled, the Control Write Sequencer will be triggered

whenever the DRC1 Signal Detect output transitions (high or low). The applicable start index location

within the sequencer memory is separately configurable for each logic condition.

The WSEQ_DRC1_SIG_DET_RISE_SEQ_INDEX register defines the sequencer start index

corresponding to a DRC1 Signal Detect Rising Edge event, as described in Table 119. The

WSEQ_DRC1_SIG_DET_FALL_SEQ_INDEX

defines

the

sequencer

start

index

corresponding to a DRC1 Signal Detect Falling Edge event.

Note that a sequencer start index of 1FFh will cause the respective sequence to be aborted.

The DRC Signal Detect sequences cannot be independently enabled for rising and falling edges.

Instead, a start index of 1FFh can be used to disable the sequence for either edge, if required.

The DRC Signal Detect control sequences are undefined following Power-On Reset (POR), but can

be user-programmed after power-up. Note that all control sequences are maintained in the sequencer

memory through Hardware Reset, Software Reset and in Sleep mode.

See “Digital Core” for further details of the Dynamic Range Control (DRC) function.

WM8281ECS/R Datenblatt(PDF) 299 Page - Cirrus Logic

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