WM8281ECSSLASHR datasheet(314/392 Pages) CIRRUS

314 / 392 page

WM8281

314

Rev 4.0

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1184

(04A0h)

HP1 Short

Circuit Ctrl

HP1_SC_ENA

HPOUT1 Short Circuit Detect Enable

0 = Disabled

1 = Enabled

R1185

(04A1h)

HP2 Short

Circuit Ctrl

HP2_SC_ENA

HPOUT2 Short Circuit Detect Enable

0 = Disabled

1 = Enabled

R1186

(04A2h)

HP3 Short

Circuit Ctrl

HP3_SC_ENA

HPOUT3 Short Circuit Detect Enable

0 = Disabled

1 = Enabled

Table 127 Headphone Short Circuit Detection Control

The Thermal Shutdown and Short Circuit protection status flags can be output directly on a GPIO pin

as an external indication of the associated events. See

“General Purpose Input / Output” to configure

a GPIO pin for this function.

POWER-ON RESET (POR)

The WM8281 will remain in the reset state until AVDD, DBVDD1 and DCVDD are all above their

respective reset thresholds. Note that specified device performance is not assured outside the voltage

ranges defined in the “Recommended Operating Conditions” section.

Refer to “Recommended Operating Conditions” for the WM8281 power-up sequencing requirements.

If DCVDD is powered from LDO1, then the DCVDD supply must be enabled using the LDOENA pin

for the initial power-up. Note that subsequent interruption to DCVDD should only be permitted as part

of a control sequence for entering Sleep mode.

After the initial power-up, the Power-On Reset will be re-scheduled following an interruption to the

DBVDD1 or AVDD supplies. Note that the AVDD supply must always be maintained whenever the

DCVDD supply is present.

If the WM8281 SLIMbus component is in its operational state, then it must be reset prior to scheduling

a Power-On Reset

. See “SLIMbus Interface Control” for details of the SLIMbus reset control

messages.

Following Power-On Reset (POR), a Boot Sequence is executed. The BOOT_DONE_STS register is

asserted on completion of the Boot Sequence, as described in Table 128. Control register writes

should not be attempted until the BOOT_DONE_STS register has been asserted.

The BOOT_DONE_STS signal is an input to the Interrupt control circuit and can be used to trigger an

Interrupt event - s

ee “Interrupts”. Under default register conditions, a falling edge on the IRQ

¯¯¯ pin will

indicate completion of the Boot Sequence.

The BOOT_DONE_STS signal can also generate a GPIO output, providing an external indication of

the Boot Sequence. See “General Purpose Input / Output” to configure a GPIO pin for this function.

For details of the Boot Sequence, s

ee “Control Write Sequencer”.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3363

(0D23h)

Interrupt

Raw

Status 5

BOOT_DONE_S

Boot Status

0 = Busy (boot sequence in progress)

1 = Idle (boot sequence completed)

Control register writes should not be

attempted until Boot Sequence has

completed.

Table 128 Device Boot-Up Status

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