WM8281ECSSLASHR datasheet(317/392 Pages) CIRRUS

317 / 392 page

WM8281

Rev 4.0

317

HARDWARE RESET, SOFTWARE RESET, WAKE-UP, AND DEVICE ID

The WM8281 provides a Hardware Reset function, which is executed whenever the RESET

¯¯¯¯¯¯ input is

asserted (logic 0). The RESET

¯¯¯¯¯¯ input is active low and is referenced to the DBVDD1 power domain.

A Hardware Reset causes most of the WM8281 control registers to be reset to their default states.

Note that the Control Write Sequencer memory and DSP firmware memory contents are retained

during Hardware Reset (assuming the conditions noted below).

An internal pull-up resistor is enabled by default on the RESET

¯¯¯¯¯¯ pin; this can be configured using the

RESET_PU register bit. A pull-down resistor is also available, as described in Table 130. When the

pull-up and pull-down resistors are both enabled, the WM8281

provides a ‘bus keeper’ function on the

RESET

¯¯¯¯¯¯ pin. The bus keeper function holds the input logic level unchanged whenever the external

circuit removes the drive (eg. if the signal is tri-stated).

If the WM8281 SLIMbus component is in its operational state, then it must be reset prior to scheduling

a Hardware Reset. See “SLIMbus Interface Control” for details of the SLIMbus reset control

messages.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3104

(0C20h)

Misc Pad

Ctrl 1

RESET_PU

RESET Pull-up enable

0 = Disabled

1 = Enabled

Note - when RESET_PD and RESET_PU

are both set to ‘1’, then a ‘bus keeper’

function is enabled on the RESET pin.

RESET_PD

RESET Pull-down enable

0 = Disabled

1 = Enabled

Note - when RESET_PD and RESET_PU

are both set to ‘1’, then a ‘bus keeper’

function is enabled on the RESET pin.

Table 130 Reset Pull-Up Configuration

A Software Reset is executed by writing any value to register R0. A Software Reset causes most of

the WM8281 control registers to be reset to their default states. Note that the Control Write Sequencer

memory and DSP firmware memory contents are retained during Software Reset (assuming the

conditions noted below).

A Wake-Up transition (from Sleep mode) is similar to a Software Reset, but selected functions and

control registers are maintained via an ‘Always-On’ internal supply domain. The ‘Always-On’ registers

are not reset during Wake-

Up. See “Low Power Sleep Configuration” for details of the ‘Always-On’

functions.

The Control Write Sequencer memory contents are retained during Hardware Reset, Software Reset

or Sleep mode; these registers are only reset following a Power-On Reset (POR).

The DSP firmware memory contents are also retained during Hardware Reset and Software Reset,

provided DCVDD is held above its reset threshold, and the DSPn_MEM_ENA bits are set to ‘1’

(default).

See the “Applications Information” section for a summary of the WM8281 memory reset conditions.

The DSPn_MEM_ENA register bits are described in Table 27.

If DCVDD is powered from LDO1, it is recommended that the LDOENA pin is asserted (logic 1) before

Hardware Reset or Software Reset; this ensures the DSP memory contents can be retained, and also

allows faster reset time.

Following Hardware Reset, Software Reset or Wake-Up (from Sleep mode), a Boot Sequence is

executed. The BOOT_DONE_STS register (see Table 128) is de-asserted during Hardware Reset,

Software Reset and in Sleep mode. The BOOT_DONE_STS register is asserted on completion of the

boot-up sequence. Control register writes should not be attempted until the BOOT_DONE_STS

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