WM8281ECSSLASHR datasheet(315/392 Pages) CIRRUS

315 / 392 page

WM8281

Rev 4.0

315

The WM8281 is in Sleep mode when AVDD and DBVDD1 are present, and DCVDD is below its reset

threshold. (Note that specific control requirements are also applicable for entering Sleep mode, as

described in “Low Power Sleep Configuration”.)

In Sleep mode, most of the Digital Core (and control registers) are held in reset; selected functions

and control registers are maintained via an ‘Always-On’ internal supply domain. See “Low Power

Sleep Configuration

” for details of the ‘Always-On’ functions.

See “Hardware Reset, Software Reset, Wake-Up, and Device ID” for details of the Wake-Up transition

(exit from Sleep mode).

Table 129 describes the default status of the WM8281 digital I/O pins on completion of Power-On

Reset, prior to any register writes. The same default conditions are also applicable on completion of a

Hardware Reset or Software Reset (see

“Hardware Reset, Software Reset, Wake-Up, and Device

”).

The same default conditions are applicable following a Wake-Up transition, except for the GPIO5,

IRQ, LDOENA, MCLK2 and RESET

¯¯¯¯¯¯

pins. These are ‘Always-On’ pins whose configuration is

unchanged in Sleep mode and during a Wake-Up transition.

Note that the default conditions described in Table 129 will not be valid if modified by the Boot

Sequence or by a

‘Wake-Up’ control sequence. See “Control Write Sequencer” for details of these

functions.

PIN NO

NAME

TYPE

RESET STATUS

MICVDD power domain

DMICCLK4

Digital Output

Digital output

DMICDAT4

Digital Input

Digital input

IN1LN / DMICCLK1

Analogue Input / Digital Output

Analogue input

IN1RN / DMICDAT1

Analogue input / Digital Input

Analogue input

IN2LN / DMICCLK2

Analogue Input / Digital Output

Analogue input

IN2RN / DMICDAT2

Analogue input / Digital Input

Analogue input

IN3LN / DMICCLK3

Analogue Input / Digital Output

Analogue input

IN3RN / DMICDAT3

Analogue input / Digital Input

Analogue input

DBVDD1 power domain

J13

AIF1BCLK

Digital Input / Output

Digital input

H13

AIF1RXDAT

Digital Input

Digital input

H12

AIF1LRCLK

Digital Input / Output

Digital input

J11

AIF1TXDAT

Digital Output

Digital output

L13

SLIMCLK

Digital Input / Output

Digital input

K12

SLIMDAT

Digital Input / Output

Digital input

F12

CIF1ADDR / CIF1SS

¯¯¯¯¯¯

Digital Input

Digital input

(Pull-down to DGND

if CIF1MODE=logic 0)

J12

CIF1MISO / GPIO4

Digital Output

Digital output

F11

CIF1MODE

Digital Input

Digital input

G13

CIF1SCLK

Digital Input

Digital input

G12

CIF1SDA / CIF1MOSI

Digital Input / Output

Digital input

H11

GPIO1

Digital Input / Output

Digital input,

Pull-down to DGND

F13

GPIO5

Digital Input / Output

Digital input,

Pull-down to DGND

E11

IRQ

¯¯¯

Digital Output

Digital output

E13

LDOENA

Digital Input

Digital input,

Pull-down to DGND

K13

MCLK1

Digital Input

Digital input

G14

MCLK2

Digital Input

Digital input

E12

RESET

¯¯¯¯¯¯

Digital Input

Digital input,

Pull-up to DBVDD1

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