THS8083APZP datasheet(45/64 Pages) TI

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5–1

5 Electrical Specifications

Electrical specifications over recommended operating conditions with Fs = 80 MSPS (unless otherwise noted)

5.1

Definition of Test Conditions

3.6

µs

800 mVPP

1/60 kHz = 16.6

µs

Figure 5–1. Input Test Waveform

Test condition SYSTEM_INTREF refers to:

•

All supplies at 3.3 V

•

XTL1_MCLK & XTL2 connected at 14.31818 MHz

•

No power downs enabled

•

XGA at 75-Hz operation mode, internal clock, clamping enabled, internal clamp timing, coarse and fine

PGAs at midscale, bottom-level clamping, clamp code at midscale, 24-bit output mode

•

Identical ac-coupled 0.8 Vpp ramp-shape input on all 3 channels at 60.0-kHz line rate, as shown in

Figure 5–1

•

Use of internal bandgap and voltage references

Test condition PLL refers to:

•

SYSTEM_INTREF, with an input signal other than the ramp-shape input test waveform of Figure 5–1.

Test condition ADC_INTREF refers to:

•

All supplies at 3.3 V

•

Use of internal bandgap and voltage references

•

Use of external ADCCLK clock (SEL_ADCCLK = 1), driven at 81.92 MHz

•

No power downs enabled

•

Identical ac-coupled, 0.8 Vpp ramp-shape input on all three channels at 60.0-kHz line rate, as shown in

Figure 5–1

Test condition ADC_EXTREF refers to:

•

ADC_INTREF, except: PWDN_BGAP = PWDN_REF = 1, VMID and VREFTO/BO driven from an external

source at nominal levels

Test condition ADC_PWDN refers to:

•

ADC_INTREF, except: PWDN_ALL = 1

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