THS8083APZP datasheet(30/64 Pages) TI

30 / 64 page

3–6

3.2.5

Subaddress: 04 (R/W)

NOM_INC23

NOM_INC22

NOM_INC21

NOM_INC20

NOM_INC19

NOM_INC18

NOM_INC17

NOM_INC16

MSB

LSB

NOM_INC[23..16]:

See register NOM_INC_0.

Default: 0x2E

3.2.6

Subaddress: 05 (R/W)

NOM_INC31

NOM_INC30

NOM_INC29

NOM_INC28

NOM_INC27

NOM_INC26

NOM_INC25

NOM_INC24

MSB

LSB

NOM_INC[31..24]:

See register NOM_INC_0.

Default: 0xBA

3.2.7

Subaddress: 06 (R/W)

NOM_INC32

MSB

LSB

NOM_INC32:

See register NOM_INC_0

Default: 0x00

NOTE: The default value for NOM_INC is 0xBA2E8A16. As shown in Appendix A, this can be calculated to

correspond to a DTO output frequency of 78.75 MHz (XGA@75Hz).

IMPORTANT: To properly update the increment, it is required to successively program NOM_INC_0 to NOM_INC_4

and then repeat the programming of the two last bytes NOM_INC3 and NOM_INC4 in this order. This properly sets

the DTO to the new frequency.

3.2.8

Subaddress: 07 (R/W)

VCODIV2

VCODIV1

VCODIV0

MSB

LSB

VCODIV[2..0]:

Divider in analog PLL loop. Determines the internal master clock frequency as VCODIV x master clock

frequency (from XTL1–MCLK/XTL2).

Default: 0x03, corresponds to an analog multiplier of 8, producing an internal nominal frequency of

8x14.31818 MHz

VCO_DIV[2..0]

ANALOG PLL MULTIPLIER

000

001

010

011 (default)

100

101

110

111

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