LMC1983CIV datasheet(3/14 Pages) NSC

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Electrical Characteristics (Continued)

The following specifications apply for V

+ = 9V, f

IN = 1 kHz, input signal (300 mV) applied to INPUT 1, volume = 0 dB, bass =

0 dB, treble = 0 dB, and loudness is off unless otherwise specified. All limits apply for T

A = TJ = +25˚C.

Symbol

Parameter

Conditions

Typical

Limit

Unit

(Note 6)

(Note 7)

(Limit)

All Volume Attenuation Settings from

Channel-to-Channel

0100010XXX100110 (76 dB) to

±0.1

±1.5

dB (min)

Tracking Error

0100010XXX000000 (0 dB)

from

0100010XXX101XXX (80 dB) to

±2.0

dB (min)

0100010XXX100111 (78 dB)

Mute Attenuation

IN = 1.0 Vrms

105

dB (max)

Bass Gain Range

IN = 100 Hz, Pins 13, 16

±12

±10.0

dB (min)

±14.0

dB (max)

Bass Tracking Error

IN = 100 Hz, Pins 13, 16

±0.1

±1.5

dB (max)

Bass Step Size

IN = 100 Hz, Pins 13, 16

2.0

1.5

dB (min)

(Relative to Previous Level)

2.5

dB (max)

Treble Gain Range

IN = 10 kHz, Pins 13, 16

±12

±10.0

dB (min)

±14.0

dB (max)

Treble Tracking Error

IN = 10 kHz, Pins 13, 16

±0.1

±1.5

dB (max)

Treble Step Size

IN = 10 kHz, Pins 13, 16

2.0

1.5

dB (min)

(Relative to Previous Level)

2.5

dB (max)

Frequency Response

IN Applied to Input 1 and Input 2;

IN = 20 Hz − 20 kHz

±0.1

±1.0

dB (max)

(Relative to Signal Amplitude at 1 kHz)

Loudness

Volume Attenuator = 40 dB, Loudness

on (See

Figure 5 )

Gain at 100 Hz (Referenced

11.5

13.5

dB (max)

to Gain at 1 kHz)

9.5

dB (min)

Gain at 10 kHz (Referenced

6.5

8.5

dB (max)

to Gain at 1 kHz)

4.5

dB (min)

Signal-to-Noise Ratio

IN = 1.0 Vrms, A Weighted,

dB (min)

Measured at 1 kHz, R

S = 470Ω

Channel Balance

All Volume Settings

0.2

1.0

dB (max)

Channel Separation

Input Pins 4, 25: Output Pins 13, 16;

dB (min)

IN = 1.0 Vrms (Note 8)

Input-Input Isolation

470

Ω to AC Ground on Unused Input

dB (min)

PSSR

Power Supply Rejection

Ratio

+ = 9V

DC; 200 mVrms, 100 Hz

Sinewave Applied to Pin 26

dB (min)

CLK

Clock Frequency

5.0

1.0

MHz (max)

IN(1)

Logic “1” Input Voltage

Pins 1, 27, 28 (IM Bus)

1.3

2.0

V (min)

Pins 2, 3

2.9

5.5

V (min)

IN(0)

Logic “0” Input Voltage

Pins 1, 27, 28 (IM Bus)

0.4

0.8

V (max)

Pins 2, 3

1.2

3.5

V (max)

OUT(1)

Logic “1” Output Voltage

Pin 28 (IM Bus)

2.0

V (min)

OUT(0)

Logic “0” Output Voltage

Pin 28 (IM Bus)

0.4

0.8

V (max)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the deivce may occur. Operating Ratings indicate conditions for which the device is func-

tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci-

fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are specified with respect to ground.

Note 3: When the input voltage (VIN) at any pin exceeds the power supply voltages (VIN < V

− or V

IN > V

+) the absolute value of the current at that pin should be

limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply voltages with 5 mA current limit to four.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature TA. The maximum

allowable power dissipation is PD = (TJMAX −TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For the LMC1983CIN, TJMAX =

+125˚C, and the typical junction-to-ambient thermal resistance, when board mounted, is 67˚C/W.

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