ST7LITEUS5 datasheet(53/136 Pages) STMICROELECTRONICS

53 / 136 page

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Power saving modes

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Figure 23.

Halt timing overview

A reset pulse of at least 42µs must be applied when exiting from Halt mode.

Figure 24.

Halt mode flowchart

WDGHALT is an option bit. See option byte section for more details.

Peripheral clocked with an external clock source can still be active.

Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 9: Interrupt mapping for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set

during the interrupt routine and cleared when the CC register is popped.

The CPU clock must be switched to 1 MHz (RC/8) or AWU RC before entering Halt mode.

Halt

Run

64 CPU CYCLE

DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

[Active-halt disabled]

HALT INSTRUCTION

RESET

INTERRUPT 3)

CPU

OSCILLATOR

PERIPHERALS 2)

IBIT

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

IBIT

OFF

X 4)

CPU

OSCILLATOR

PERIPHERALS

IBITS

X 4)

64 CPU CLOCK CYCLE

DELAY 5)

WATCHDOG

ENABLE

DISABLE

WDGHALT 1)

WATCHDOG

RESET

(Active-halt disabled)

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