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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ST7LITEUS5 Datenblatt(PDF) 66 Page - STMicroelectronics |
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ST7LITEUS5 Datenblatt(HTML) 66 Page - STMicroelectronics |
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66 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) On-chip peripherals ST7LITEUS2, ST7LITEUS5 66/136 Figure 30. Lite timer block diagram 10.1.3 Functional description The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of fOSC. A counter overflow event occurs when the counter rolls over from 1F39h to 00h. If fOSC = 8 MHz, then the time period between two counter overflow events is 1 ms. This period can be doubled by setting the TB bit in the LTCSR register. When the timer overflows, the TBF bit is set by hardware and an interrupt request is generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register. Watchdog The watchdog is enabled using the WDGE bit. The normal watchdog timeout is 2 ms (@ fosc = 8 MHz), after which it then generates a reset. To prevent this watchdog reset occurring, software must set the WDGD bit. The WDGD bit is cleared by hardware after tWDG. This means that software must write to the WDGD bit at regular intervals to prevent a watchdog reset occurring. Refer to Figure 31. If the watchdog is not enabled immediately after reset, the first watchdog timeout will be shorter than 2ms, because this period is counted starting from reset. Moreover, if a 2ms period has already elapsed after the last MCU reset, the watchdog reset will take place as soon as the WDGE bit is set. For these reasons, it is recommended to enable the watchdog immediately after reset or else to set the WDGD bit before the WGDE bit so a watchdog reset will not occur for at least 2 ms. Note: Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals. LTCSR WATCHDOG 13-bit UPCOUNTER /2 8-bit fLTIMER fWDG 8 MSB LTIC fOSC WDGD WDGE WDG TBF TBIE TB ICF ICIE WATCHDOG RESET LTTB INTERRUPT REQUEST LTIC INTERRUPT REQUEST LTICR INPUT CAPTURE REGISTER 1 0 1 or 2 ms Timebase (@ 8MHz fOSC) To 12-bit AT TImer fLTIMER RF 0 7 Obsolete Product(s) - Obsolete Product(s) |
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