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WM8523 Datenblatt(PDF) 10 Page - Cirrus Logic |
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WM8523 Datenblatt(HTML) 10 Page - Cirrus Logic |
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10 / 46 page ![]() WM8523 Production Data w PD, Rev 4.2, August 2013 10 AUDIO INTERFACE TIMING – SLAVE MODE Figure 3 Digital Audio Data Timing – Slave Mode Test Conditions LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25 °C, Slave Mode PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 27 ns BCLK pulse width high tBCH 11 ns BCLK pulse width low tBCL 11 ns LRCLK set-up time to BCLK rising edge tLRSU 7 ns LRCLK hold time from BCLK rising edge tLRH 5 ns DACDAT hold time from LRCLK rising edge tDH 5 ns DACDAT set-up time to BCLK rising edge tDS 7 ns Table 2 Slave Mode Audio Interface Timing Note: BCLK period should always be greater than or equal to MCLK period. |
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