WM8523 datasheet(16/46 Pages) CIRRUS

16 / 46 page

WM8523

Production Data

PD, Rev 4.2, August 2013

2C CONTROL MODE

In I

2C mode, the WM8523 is a slave device on the control interface; SCLK is a clock input, while SDA is a

bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same

interface, the WM8523 transmits logic 1 by tri-stating the SDA pin, rather than pulling it high. An external

pull-up resistor is required to pull the SDA line high so that the logic 1 can be recognised by the master.

In order to allow many devices to share a single I

2C control bus, every device on the bus has a unique 7-

bit device address (this is not the same as the 8-bit address of each register in the WM8523). The device

address is determined by the logic level on the SDOUT and CS

¯¯ pins as shown in Table 7. The LSB of the

device address is the R/W

¯¯ bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”.

SDOUT

ADDR1

¯¯

ADDR0

DEVICE ADDRESS

0011 0100 (34h)

0011 0110 (36h)

0011 1100 (3Ch)

0011 1110 (3Eh)

Table 7 Control Interface Device Address Selection

The WM8523 operates as an I

2C slave device only. The controller indicates the start of data transfer with

a high to low transition on SDA while SCLK remains high. This indicates that a device address, register

address and data will follow. All devices on the I

2C bus respond to the start condition and shift in the next

eight bits on SDA (7-bit device address + Read/Write bit, MSB first). If the device address received

matches the device address of the WM8523, then the WM8523 responds by pulling SDA low on the next

clock pulse (ACK). If the device address is not recognised or the R/W

¯¯ bit is ‘1’ when operating in write

only mode, the WM8523 returns to the idle condition and waits for a new start condition and valid

address.

If the device address matches the device address of the WM8523, the data transfer continues as

described below. The controller indicates the end of data transfer with a low to high transition on SDA

while SCLK remains high. After receiving a complete address and data sequence the WM8523 returns to

the idle state and waits for another start condition. If a start or stop condition is detected out of sequence

at any point during data transfer (i.e. SDA changes while SCLK is high), the device returns to the idle

condition.

The WM8523 supports the following read and write operations:



Single write



Single read

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