WM8523 datasheet(18/46 Pages) CIRRUS

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WM8523

Production Data

PD, Rev 4.2, August 2013

SPI CONTROL MODE

The WM8523 can also be controlled by writing to registers through a SPI control interface. A control word

consists of 24 bits. The first bit is the read/write bit (R/W

¯¯), which is followed by 7 address bits (A6 to A0)

that determine which control register is accessed. The remaining 16 bits (B15 to B0) are data bits,

corresponding to the 16 bits in each control register.

Volume update registers R06h and R07h are unavailable in SPI control mode. To use volume update in

software control mode, I

2C mode must be used.

In SPI mode, every rising edge of SCLK clocks in one data bit from the SDA pin. A rising edge on CS

¯¯

latches in a complete control word consisting of the last 24 bits.

The SPI mode write operation protocol is illustrated in Figure 12.

Figure 12 SPI Control Interface – write operation

In Write operations (R/W

¯¯=0), all SDA bits are driven by the controlling device.

In Read operations (R/W

¯¯=1), the SDA pin is ignored following receipt of the valid register address. The

data bits are output by the WM8523 on the SDOUT pin.

The SPI mode read operation protocol is illustrated in Figure 13.

Figure 13 SPI Control Interface – read operation

Any write to register R0 (00h) will reset the WM8523. All register bits are reset to their default values.

DEVICE ID AND REVISION

Reading from register R0 (00h) returns the device ID. Reading from register R1 returns the device

revision number.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DEVICE_ID

00h

15:0

DEVICE_ID

[15:0]

10000101

00100011

Device ID

A read of this register will return the device

ID, 0x8523.

REVISION

01h

2:0

CHIP_REV

[2:0]

N/A

Device Revision

A read of this register will return the device

revision number. This number is

sequentially incremented if the device design

is updated.

Table 8 Device ID and Revision Number

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