AD9689-2000EBZ datasheet(71/134 Pages) AD

71 / 134 page

Data Sheet

AD9689

Rev. A | Page 71 of 134

DIGITAL OUTPUTS

INTRODUCTION TO THE JESD204B INTERFACE

The AD9689 digital outputs are designed to the JEDEC standard

JESD204B, serial interface for data converters. JESD204B is a

protocol to link the AD9689 to a digital processing device over a

serial interface with lane rates of up to 16 Gbps. The benefits of

the JESD204B interface over LVDS include a reduction in

required board area for data interface routing and an ability to

enable smaller packages for converter and logic devices.

JESD204B OVERVIEW

The JESD204B data transmit block assembles the parallel data

from the ADC into frames and uses 8-bit/10-bit encoding as

well as optional scrambling to form serial output data. Lane

synchronization is supported through the use of separate

control characters during the initial establishment of the link.

Additional control characters are embedded in the data stream

to maintain synchronization thereafter. A JESD204B receiver is

required to complete the serial link. For additional details on

the JESD204B interface, refer to the JESD204B standard.

The AD9689 JESD204B data transmit block maps up to two

physical ADCs or up to eight virtual converters (when DDCs are

enabled) over a link. A link can be configured to use one, two,

four, or eight JESD204B lanes. The JESD204B specification refers

to a number of parameters to define the link, and these parameters

must match between the JESD204B transmitter (the AD9689

output) and the JESD204B receiver (the logic device input).

The JESD204B link is described according to the following

parameters:

•

L is the number of lanes per converter device (lanes per

link); AD9689 value = 1, 2, 4, or 8.

•

M is the number of converters per converter device (virtual

converters per link); AD9689 value = 1, 2, 4, or 8.

•

F is the octets per frame; AD9689 value = 1, 2, 4, 8, or 16.

•

N΄ is the number of bits per sample (JESD204B word size);

AD9689 value = 8 or 16.

•

N is the converter resolution; AD9689 value = 7 to 16.

•

CS is the number of control bits per sample;

AD9689 value = 0, 1, 2, or 3.

•

K is the number of frames per multiframe;

AD9689 value = 4, 8, 12, 16, 20, 24, 28, or 32.

•

S is the samples transmitted per single converter per frame

cycle; AD9689 value is set automatically based on L, M, F,

and N΄.

•

HD is the high density mode; the AD9689 mode is set

automatically based on L, M, F, and N΄.

•

CF is the number of control words per frame clock cycle

per converter device; AD9689 value = 0.

Figure 131 shows a simplified block diagram of the AD9689

JESD204B link. By default, the AD9689 is configured to use

two converters and eight lanes. Converter A data is output to

SERDOUT0±, SERDOUT1±, SERDOUT2± and SERDOUT3±;

and Converter B is output to SERDOUT4±, SERDOUT5±,

SERDOUT6±, and SERDOUT7±. The AD9689 allows other

configurations, such as combining the outputs of both

converters onto a single lane, or changing the mapping of the

A and B digital output paths. These modes are set up via the SPI

By default in the AD9689, the 14-bit converter word from each

converter is broken into two octets (eight bits of data). Bit 13

(MSB) through Bit 6 are in the first octet. The second octet

contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits

can be configured as zeros or as a pseudorandom number

sequence. The tail bits can also be replaced with control bits

indicating overrange, SYSREF±, or fast detect output.

The two resulting octets can be scrambled. Scrambling is

optional; however, it is recommended to avoid spectral peaks

when transmitting similar digital data patterns. The scrambler

uses a self synchronizing, polynomial-based algorithm defined

by the equation 1 + x14 + x15. The descrambler in the receiver is

a self synchronizing version of the scrambler polynomial.

The two octets are then encoded with an 8-bit/10-bit encoder. The

8-bit/10-bit encoder works by taking eight bits of data (an octet)

and encoding them into a 10-bit symbol. Figure 132 shows how

the 14-bit data is taken from the ADC, how the tail bits are added,

how the two octets are scrambled, and how the octets are encoded

into two 10-bit symbols. Figure 132 shows the default data format.

MUX/

FORMAT

(SPI

REGISTERS

0x0561,

0x0564)

JESD204B LINK

CONTROL

(L, M, F)

(SPI REGISTER

0x058B,

0x058E, 0x058C)

LANE MUX

AND

MAPPING

(SPI

REGISTERS

0x05B0,

0x05B2,

0x05B3,

0x05B5,

0x05B6)

CONVERTER A

INPUT

ADC A

CONVERTER B

CONVERTER 0

CONVERTER 1

INPUT

SYSREF±

SERDOUT0±

SERDOUT7±

SERDOUT6±

SERDOUT5±

SERDOUT4±

SERDOUT3±

SERDOUT2±

SERDOUT1±

SYNCINB±

ADC B

Figure 131. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x0200 = 0x00)

AD9689-2000EBZ Datenblatt(PDF) 71 Page - Analog Devices

AD9689-2000EBZ Datenblatt(HTML) 71 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL