AD9689-2000EBZ datasheet(2/134 Pages) AD

2 / 134 page

AD9689

Data Sheet

Rev. A | Page 2 of 134

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

General Description ......................................................................... 4

Product Highlights ........................................................................... 4

Specifications..................................................................................... 5

DC Specifications ......................................................................... 5

AC Specifications.......................................................................... 6

Digital Specifications ................................................................... 8

Switching Specifications .............................................................. 9

Timing Specifications ................................................................ 10

Absolute Maximum Ratings.......................................................... 12

Thermal Resistance .................................................................... 12

ESD Caution................................................................................ 12

Pin Configuration and Function Descriptions........................... 13

Typical Performance Characteristics ........................................... 16

2.0 GSPS....................................................................................... 16

2.6 GSPS....................................................................................... 21

Equivalent Circuits ......................................................................... 26

Theory of Operation ...................................................................... 28

ADC Architecture ...................................................................... 28

Analog Input Considerations.................................................... 28

Voltage Reference ....................................................................... 31

DC Offset Calibration................................................................ 32

Clock Input Considerations ...................................................... 32

Power-Down and Standby Mode ............................................. 35

Temperature Diode .................................................................... 35

ADC Overrange and Fast Detect.................................................. 37

ADC Overrange.......................................................................... 37

Fast Threshold Detection (FD_A and FD_B) ........................ 37

ADC Application Modes and JESD204B Tx Converter Mapping

........................................................................................................... 38

Programmable FIR Filters ............................................................. 40

Supported Modes........................................................................ 40

Programming Instructions........................................................ 42

Digital Downconverter (DDC)..................................................... 44

DDC I/Q Input Selection .......................................................... 44

DDC I/Q Output Selection ....................................................... 44

DDC General Description ........................................................ 44

DDC Frequency Translation..................................................... 47

DDC Decimation Filters ........................................................... 55

DDC Gain Stage ......................................................................... 61

DDC Complex to Real Conversion ......................................... 61

DDC Mixed Decimation Settings ............................................ 62

DDC Example Configurations ................................................. 64

DDC Power Consumption........................................................ 67

Signal Monitor ................................................................................ 68

SPORT over JESD204B.............................................................. 69

Digital Outputs ............................................................................... 71

Introduction to the JESD204B Interface ................................. 71

JESD204B Overview .................................................................. 71

Functional Overview ................................................................. 72

JESD204B Link Establishment ................................................. 72

Physical Layer (Driver) Outputs .............................................. 74

fS × 4 Mode .................................................................................. 75

Setting Up the AD9689 Digital Interface................................. 76

Deterministic Latency.................................................................... 83

Subclass 0 Operation.................................................................. 83

Subclass 1 Operation.................................................................. 83

Multichip Synchronization............................................................ 85

Normal Mode.............................................................................. 85

Timestamp Mode ....................................................................... 85

SYSREF Input.............................................................................. 87

SYSREF± Setup/Hold Window Monitor................................. 89

Latency............................................................................................. 91

End to End Total Latency.......................................................... 91

Example Latency Calculations.................................................. 91

LMFC Referenced Latency........................................................ 91

Test Modes....................................................................................... 93

ADC Test Modes ........................................................................ 93

JESD204B Block Test Modes .................................................... 94

Serial Port Interface........................................................................ 96

Configuration Using the SPI..................................................... 96

Hardware Interface..................................................................... 96

SPI Accessible Features.............................................................. 96

Memory Map .................................................................................. 97

Reading the Memory Map Register Table............................... 97

Memory Map Register Details.................................................. 98

Applications Information ............................................................ 132

AD9689-2000EBZ Datenblatt(PDF) 2 Page - Analog Devices

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