AD9689-2000EBZ datasheet(87/134 Pages) AD

87 / 134 page

Data Sheet

AD9689

Rev. A | Page 87 of 134

SYSREF INPUT

The SYSREF input signal is used as a high accuracy system

reference for deterministic latency and multichip synchro-

nization. The AD9689 accepts a single-shot or periodic input

signal. The SYSREF± mode select bits (Register 0x0120, Bits[2:1])

select the input signal type and arm the SYSREF state machine

when set. If in single (or N) shot mode (Register 0x0120, Bits[2:1]

= 2 decimal), the SYSREF± mode select bit self clears after the

appropriate SYSREF transition is detected. The pulse width

must have a minimum width of two CLK± periods. If the clock

divider (Register 0x010B, Bits[3:0]) is set to a value other than

divide by 1, multiply this minimum pulse width requirement by

the divide ratio (that is, if set to divide by 8, the minimum pulse

width is 16 CLK± cycles). When using a continuous SYSREF

signal (Register 0x0120, Bits[2:1] = 1 decimal), the period of the

SYSREF signal must be an integer multiple of the LMFC. LMFC

can be derived using the following formula:

LMFC = ADC clock/(S × K)

where:

S is the JESD204B parameter for number of samples per converter.

K is the number of frames per multiframe.

The input clock divider, DDCs, signal monitor block, and

JESD204B link are all synchronized using the SYSREF± input when

in normal synchronization mode (Register 0x01FF, Bit 0 = 0).

The SYSREF± input can also be used to timestamp an ADC

sample to provide a mechanism for synchronizing multiple

AD9689 devices in a system. For the highest level of timing

accuracy, SYSREF± must meet setup and hold requirements

relative to the CLK± input. There are several features in the

AD9689 that can be used to ensure these requirements are met;

these features are described in the SYSREF Control Features

section.

SYSREF Control Features

SYSREF is used, along with the input clock (CLK), as part of a

source-synchronous timing interface and requires setup and

hold timing requirements of −65 ps and 95 ps relative to the

input clock (see Figure 148). The AD9689 has several features

that aid the user in meeting these requirements. First, the

SYSREF sample event can be defined as either a synchronous

low to high transition or synchronous high to low transition.

Second, the AD9689 allows the SYSREF signal to be sampled

using either the rising edge or falling edge of the input clock.

Figure 148, Figure 149, Figure 150, and Figure 151 show all four

possible combinations.

The third SYSREF related feature available is the ability to

ignore a programmable number (up to 16) of SYSREF events.

The AD9689 is able to ignore N SYSREF events (note that the

SYSREF ignore feature is enabled by setting the SYSREF± mode

select bits (Register 0x0120, Bits[2:1]) to 2'b10, N-shot mode).

This feature is useful for handling periodic SYSREF signals,

which need time to settle after startup. Ignoring SYSREF until the

clocks in the system have settled can avoid an inaccurate SYSREF

trigger. Figure 152 shows an example of the SYSREF ignore

feature when ignoring three SYSREF events.

CLK

SYSREF

KEEP OUT WINDOW

SYSREF

SAMPLE POINT

HOLD

REQUIREMENT

95ps

SETUP

REQUIREMENT

–65ps

Figure 148. SYSREF Setup and Hold Time Requirements—SYSREF Low to

High Transition Using Rising Edge Clock (Default)

CLK

SYSREF

SAMPLE POINT

HOLD

REQUIREMENT

95ps

SETUP

REQUIREMENT

–65ps

Figure 149. SYSREF Low to High Transition Using Falling Edge Clock Capture

(Register 0x0120, Bit 4 = 1’b0; Register 0x0120, Bit 3 = 1’b1)

CLK

SYSREF

SAMPLE POINT

HOLD

REQUIREMENT

95ps

SETUP

REQUIREMENT

–65ps

Figure 150. SYSREF High to Low Transition Using Rising Edge Clock Capture

(Register 0x0120, Bit 4 = 1’b1; Register 0x0120, Bit 3 = 1’b0)

SYSREF

SAMPLE POINT

CLK

SYSREF

HOLD

REQUIREMENT

95ps

SETUP

REQUIREMENT

–65ps

Figure 151. SYSREF High to Low Transition Using Falling Edge Clock Capture

(Register 0x0120, Bit 4 = 1’b1; Register 0x0120, Bit 3 = 1’b1)

AD9689-2000EBZ Datenblatt(PDF) 87 Page - Analog Devices

AD9689-2000EBZ Datenblatt(HTML) 87 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL