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LT1952

1952f

RBLANK

(MIN)

= 10k

10k < RBLANK ≤ 240k

100ns

(AUTOMATIC)

LEADING

EDGE

BLANKING

(PROGRAMMABLE)

EXTENDED

BLANKING

CURRENT

SENSE

DELAY

OUT

BLANKING

1952 F06

Xns

X + 45ns

[X + 45(RBLANK/10k)]ns

APPLICATIO S I FOR ATIO

Blanking is provided in 2 phases (Figure 6): The first phase

automatically blanks during gate rise time. Gate rise times

can vary depending on MOSFET type. For this reason the

LT1952 performs true ‘leading edge blanking’ by auto-

matically blanking OC and ISENSE comparator outputs until

OUT rises to within 0.5V of VIN or reaches its clamp level

of 13V. The second phase of blanking starts after the

leading edge of OUT has been completed. This phase is

programmable by the user with a resistor connected from

the BLANK pin to ground. Typical durations for this portion

of the blanking period are from 45ns at RBLANK = 10k to

540ns at RBLANK = 120k. Blanking duration can be approxi-

mated as:

Blanking (extended) = [45(RBLANK/10k)]ns

(see graph in Typical Performance Characteristics)

Figure 6. Leading Edge Blank Timing

Figure 7. Programming Slope Compensation

Programming Current Limit (OC Pin)

The LT1952 uses a precise 100mV sense threshold at the

OC pin to detect over-current conditions in the converter

and set a soft-start latch. It is independent of duty cycle

because it is not affected by slope compensation pro-

grammed at the ISENSE pin. The OC pin monitors the peak

current in the primary MOSFET by sensing the voltage

across a sense resistor (RS) in the source of the MOSFET.

The current limit for the converter can be programmed by,

Current limit = (100mV/RS)(NP/NS) – (1/2)(IRIPPLE)

where,

RS = sense resistor in source of primary MOSFET

IRIPPLE = p-p ripple current in the output inductor L1

NS = number of transformer secondary turns

NP = number of transformer primary turns

Programming Slope Compensation

The LT1952 uses a current mode architecture to provide

fast response to load transients and to ease frequency

compensation requirements. Current mode switching regu-

lators which operate with duty cycles above 50% and have

continuous inductor current must add slope compensa-

tion to their current sensing loop to prevent subharmonic

oscillations. (For more information on slope compensa-

tion, see Application Note 19.) The LT1952 has program-

mable slope compensation to allow a wide range of

inductor values, to reduce susceptibility to PCB generated

noise and to optimize loop bandwidth. The LT1952 pro-

grams slope compensation by inserting a resistor RSLOPE

in series with the ISENSE pin (Figure 7). The LT1952

generates a current at the ISENSE pin which is linear from

0% duty cycle to the maximum duty cycle of the OUT pin.

A simple calculation of I(ISENSE) • RSLOPE gives an added

ramp to the voltage at the ISENSE pin for programmable

slope compensation. (See both graphs ‘ISENSE Pin Current

vs. Duty Cycle’ and ‘ISENSE Maximum Threshold vs Duty

Cycle’ in the Typical Performance Characteristics

section.)

CURRENT SLOPE = 35µA • DC

V(ISENSE) = VS + (ISENSE • RSLOPE)

ISENSE = 8µA + 35DC µA

DC = DUTY CYCLE

FOR SYNC OPERATION

ISENSE(SYNC) = 8µA + (k • 35DC)µA

k = fOSC/fSYNC

1952 F07

ISENSE

OUT

LT1952

RSLOPE

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