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LT1952

1952f

APPLICATIO S I FOR ATIO

to give,

t = RC • (–1) • ln(1 – VSS/SS_MAXDC(DC))

where,

VSS = SS_MAXDC voltage at time t

SS_MAXDC(DC) = programmed DC voltage setting

maximum duty cycle clamp =

VREF(RB/(RT + RB)

R = RCHARGE (Figure 11) = RT • RB/(RT + RB)

C = CSS (Figure 11)

Example (1) No Switching Period

The period of no switching for the converter, when a

soft-start event has occurred, depends on how far

SS_MAXDC can fall before recharging occurs and how

long a fault exists. It will be assumed that a fault triggering

soft-start is removed before SS_MAXDC can reach its

reset threshold (0.45V).

No Switching Period = tDISCHARGE + tCHARGE

tDISCHARGE = discharge time from SS_MAXDC(DC) to

0.45V

tCHARGE = charge time from 0.45V to VSS(ACTIVE)

tDISCHARGE was already calculated earlier as 185µs.

tCHARGE is calculated by assuming the following:

VREF = 2.5V, RT = 35.7k, RB = 100k, CSS = 0.1µF and

VSS(MIN) = 0.45V.

tCHARGE = t(VSS = 0.8V) – t(VSS = 0.45V)

Step 1:

SS_MAXDC(DC) = 2.5[100k/(35.7k + 100k)] = 1.84V

RCHARGE = (35.7k • 100k/135.7k) = 26.3k

Step 2:

t(VSS = 0.45V) is calculated from,

t = RCHARGE • CSS • (–1) • ln(1 – VSS/SS_MAXDC(DC))

= 2.63e4 • 1e–7 • (–1) • ln(1 – 0.45/1.84)

= 2.63e–3 • (–1) • ln(0.755) = 7.3e–4 s

Step 3:

t(VSS = 0.8V) is calculated from,

t = RCHARGE • CSS • (–1) • ln(1 – VSS/SS_MAXDC(DC))

= 2.63e4 • 1e–7 • (–1) • ln(1 – 0.8/1.84)

= 2.63e–3 • (–1) • ln(0.565) = 1.5e–3 s

From Step 1 and Step 2

tCHARGE = (1.5 – 0.73)e–3 s = 7.7e–4 s

The total time of no switching for the converter due to a

soft-start event

= tDISCHARGE + tCHARGE = 1.85e–4 + 7.7e–4 = 9.55e–4 s

Example (2) Converter Output Rise Time

The rise time for the converter output to reach regulation

can be closely approximated as the time between the start

of switching (SS_MAXDC = VSS(ACTIVE)) and the time

where converter duty cycle is in regulation (DC(REG)) and

no longer controlled by SS_MAXDC (SS_MAXDC =

VSS(REG)). Converter output rise time can be expressed as,

Output Rise Time = t(VSS(REG)) – t(VSS(ACTIVE))

Step 1: Determine converter duty cycle DC(REG) for

output in regulation

The natural duty cycle DC(REG) of the converter depends

on several factors. For this example it is assumed that

DC(REG) = 60% for system input voltage near the

undervoltage lockout threshold (UVLO). This gives

SD_VSEC = 1.32V.

Also assume that the maximum duty cycle clamp pro-

grammed for this condition is 72% for SS_MAXDC(DC) =

1.84V, fOSC = 200kHz and RDELAY = 40k.

Step 2: Calculate VSS(REG)

To calculate the level of SS_MAXDC (VSS(REG)) that no

longer clamps the natural duty cycle of the converter, the

equation for maximum duty cycle clamp must be used

(see previous section ‘Programming Maximum Duty Cycle

Clamp’).

The point where the maximum duty cycle clamp meets

DC(REG) during soft-start is given by,

DC(REG) = Max Duty Cycle clamp

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