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LT1952

1952f

APPLICATIO S I FOR ATIO

Programming Synchronous Rectifier Timing:

SOUT to OUT delay (‘tDELAY’)

The LT1952 has an additional output SOUT which pro-

vides a ±50mA peak drive clamped to 12V. In applications

requiring synchronous rectification for high efficiency, the

LT1952 SOUT provides a sync signal for secondary side

control of the synchronous rectifier MOSFETs (Figure11).

Timing delays through the converter can cause non-

optimum control timing for the synchronous rectifier

MOSFETs. The LT1952 provides a programmable delay

(tDELAY, Figure 8) between SOUT rising edge and OUT

rising edge to optimize timing control for the synchronous

rectifier MOSFETs to achieve maximum efficiency gains. A

resistor RDELAY connected from the DELAY pin to ground

sets the value of tDELAY. Typical values for tDELAY range

from 10ns with RDELAY = 10k to 160ns with RDELAY = 160k.

(see graph in Typical Performance Characteristics)

Figure 9. Programming Maximum Duty Cycle Clamp

SS_MAXDC pin using a resistor divider from VREF. An

increase of voltage at the SS_MAXDC pin causes the

maximum duty cycle clamp to increase.

To program the volt-second clamp, the following steps

should be taken:

(1) The maximum operational duty cycle of the converter

should be calculated for the given application.

(2) An initial value for the maximum duty cycle clamp

should be calculated using the equation below with a

first pass guess for SS_MAXDC.

Note: Since maximum operational duty cycle occurs at

minimum system input voltage (UVLO), the voltage at the

SD_VSEC pin = 1.32V.

Max Duty Cycle Clamp (OUT pin)

= k • 0.522(SS_MAXDC(DC)/SD_VSEC) –

(tDELAY • fOSC)

where,

SS_MAXDC(DC) = VREF(RB/(RT + RB)

SD_VSEC = 1.32V at minimum system input voltage

tDELAY = programmed delay between SOUT and OUT

k = 1.11 – 5.5e–7 • (fOSC)

(3) The maximum duty cycle clamp calculated in (2)

should be programmed to be 10% greater than the

maximum operational duty cycle calculated in (1). Simple

adjustment of maximum duty cycle can be achieved by

adjusting SS_MAXDC.

Figure 8. Programming SOUT to OUT Delay: tDELAY

1952 F08

DELAY

LT1952

RDELAY

tDELAY

SOUT

OUT

SYSTEM

INPUT VOLTAGE

ADAPTIVE

DUTY CYCLE

CLAMP INPUT

MAX DUTY CYCLE

CLAMP ADJUST INPUT

*MINIMUM ALLOWABLE RT IS 10k TO

GUARANTEE SOFT-START PULL-OFF

1952 F09

SD_VSEC

SS_MAXDC

VREF

LT1952

RT*

Programming Maximum Duty Cycle Clamp

For forward converter applications using the simplest

topology of a single MOSFET on the primary, a maximum

switch duty cycle clamp which adapts to transformer input

voltage is necessary for reliable control of the MOSFET.

This volt-second clamp provides a safeguard for trans-

former reset that prevents transformer saturation. The

LT1952 SD_VSEC and SS_MAXDC pins provide a capaci-

tor-less, programmable volt-second clamp solution using

simple resistor ratios (Figure 9).

An increase of voltage at the SD_VSEC pin causes the

maximum duty cycle clamp to decrease. Deriving SD_VSEC

from a resistor divider connected to system input voltage

creates the volt-second clamp. The maximum duty cycle

clamp can be adjusted by programming voltage on the

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