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LTC4449 Datenblatt(PDF) 21 Page - Linear Technology |
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LTC4449 Datenblatt(HTML) 21 Page - Linear Technology |
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21 / 38 page ![]() LTC3774 21 3774fc For more information www.linear.com/LTC3774 size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires moreturnsofwireandthereforecopperlosseswillincrease. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that induc- tance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! PWM and PWMEN Pins The PWM pins are three-state compatible outputs, de- signed to drive MOSFET drivers, DrMOSs, etc which do not represent a heavy capacitive load. An external resistor divider may be used to set the voltage to mid-rail while in the high impedance state. ThePWMENoutputshaveanopen-drainpull-uptoINTVCC and require an appropriate external pull-down resistor. This pin is intended to drive the enable pins of the MOS- FET drivers that do not have three-state compatible PWM inputs. PWMEN is low only when PWM is high impedance, and high at any other PWM state. When selecting a DrMOS or gate driver to use with the LTC3774, care must be taken to ensure that the absolute maximum voltage rating for the DrMOS or gate driver’s PWM input is not exceeded. The LTC3774’s PWM output driver is biased from INTVCC, which is typically 5.5V, while the DrMOS or gate driver is generally biased from a 5V supply. If the DrMOS or gate driver has a maximum PWM rating less than 5.5V then tie the VIN and INTVCC pins of the LTC3774 together and tie the combined pins to the 5V supply with a 1Ω or 2.2 Ω resistor. Please a 4.4µF capacitor from the combined VIN and INTVCC pins to ground. Refer to Figure 11 for an example. Contact factory applications support for assistance. APPLICATIONS INFORMATION Power MOSFET and Schottky Diode (Optional) Selection At least two external power MOSFETs need to be selected: One N-channel MOSFET for the top (main) switch and one or more N-channel MOSFET(s) for the bottom (synchro- nous) switch. The number, type and on-resistance of all MOSFETsselectedtakeintoaccountthevoltagestep-down ratio as well as the actual position (main or synchronous) in which the MOSFET will be used. A much smaller and much lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output voltage that is less than one-third of the input voltage. In applications where VIN >> VOUT, the top MOSFETs’ on- resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purposedevicesthatprovidereasonablylowon-resistance with significantly reduced input capacitance for the main switch application in switching regulators. The peak-to-peak MOSFET gate drive levels are set by the internal regulator voltage, VINTVCC, requiring the use of logic-level threshold MOSFETs in most applications. Pay close attention to the BVDSSspecificationfortheMOSFETs as well; many of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the on-resistance, RDS(ON), input capacitance, inputvoltageandmaximumoutputcurrent.MOSFETinput capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets (Figure 8). The curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. Figure 8. Gate Charge Characteristic + – VDS VIN 3774 F08 VGS MILLER EFFECT QIN a b CMILLER = (QB – QA)/VDS VGS V + – |
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