LTC4449 datasheet(27/38 Pages) LINER

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LTC3774

3774fc

For more information www.linear.com/LTC3774

Figure 12. Relationship Between Oscillator

Frequency and Voltage at the FREQ Pin

Figure 13. Phase-Locked Loop Block Diagram

VFREQ (V)

0.4

900

1100

1300

1.0

1.4

3774 F12

700

500

0.6

0.8

1.2

1.6

1.8

300

100

DIGITAL

PHASE/

FREQUENCY

DETECTOR

VCO

2.4V 5.5V

20µA

RSET

3774 F13

FREQ

SYNC

EXTERNAL

OSCILLATOR

MODE/PLLIN

APPLICATIONS INFORMATION

If the external clock frequency is greater than the inter-

nal oscillator’s frequency, fOSC, then current is sourced

continuously from the phase detector output, pulling up

the filter network. When the external clock frequency is

less than fOSC, current is sunk continuously, pulling down

the filter network. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. The voltage on the filter network is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the filter capacitor CLP holds the voltage.

Typically,theexternalclock(ontheMODE/PLLINpin)input

high threshold is 1.6V, while the input low threshold is 1V.

Using the CLKOUT and PHSMD Pins in Multiphase

Applications

The LTC3774 features CLKOUT and PHSMD pins that

allow multiple LTC3774 ICs to be daisy chained together

in multiphase applications. The clock output signal on the

CLKOUT pin can be used to synchronize additional ICs in

a 3-, 4-, 6-, 8- or 12-phase power supply solution feeding

a single high current output, or even several outputs from

the same input supply.

The PHSMD pin is used to adjust the phase relationship

between channel 1 and channel 2, as well as the phase

relationship between channel 1 and CLKOUT. The phases

are calculated relative to zero degrees, defined as the rising

edgeofPWM1.RefertotheApplicationsInformationsection

for more details on how to create multiphase applications.

Minimum On-Time Considerations

Minimum on-time, tON(MIN), is the smallest time duration

that the LTC3774 is capable of turning on the top MOSFET.

It is determined by internal timing delays, power stage

timing delays and the gate charge required to turn on the

top MOSFET. Low duty cycle applications may approach

this minimum on-time limit and care should be taken to

ensure that:

tON(MIN) <

VOUT

VIN f()

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the voltage ripple and current ripple will increase.

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