LTC4449 datasheet(30/38 Pages) LINER

30 / 38 page

LTC3774

3774fc

For more information www.linear.com/LTC3774

2. Placethefeedbackdividerbetweenthe+and–terminals

of COUT. Route VOSNS+ and VOSNS– with minimum PC

trace spacing from the IC to the feedback divider.

3. Are the SNSA+, SNSD+ and SNS– printed circuit traces

routed together with minimum PC trace spacing? The

filter capacitors between SNSA+, SNSD+ and SNS–

should be as close as possible to the pins of the IC.

4. Do the (+) plates of CIN connect to the drain of the

topside MOSFET as closely as possible? This capacitor

provides the pulsed current to the MOSFET.

5. Keep the switching nodes away from sensitive small-

signal nodes (SNSD+, SNSA+, SNS–, VOSNS+, VOSNS–).

Ideally the PWM and switch nodes printed circuit traces

should be routed away and separated from the IC and

especially the quiet side of the IC. Separate the high dv/

dttracesfromsensitivesmall-signalnodeswithground

traces or ground planes.

6. Use a low impedance source such as a logic gate to

drive the MODE/PLLIN pin and keep the lead as short

as possible.

7. The 47pF to 330pF ceramic capacitor between the ITH

pin and signal ground should be placed as close as

possible to the IC. Figure 14 illustrates all branch cur-

rents in a switching regulator. It becomes very clear

after studying the current waveforms why it is critical to

keepthehighswitchingcurrentpathstoasmallphysical

size. High electric and magnetic fields will radiate from

these loops just as radio stations transmit signals. The

output capacitor ground should return to the negative

terminal of the input capacitor and not share a com-

mon ground path with any switched current paths. The

left half of the circuit gives rise to the

noise generated

by a switching regulator. The ground terminations of

the synchronous MOSFET and Schottky diode should

return to the bottom plate(s) of the input capacitor(s)

with a short isolated PC trace since very high switched

currents are present. External OPTI-LOOP® compensa-

tion allows overcompensation for PC layouts which are

not optimized but this is not the recommended design

procedure.

APPLICATIONS INFORMATION

Figure 14. Branch Current Waveforms

RIN

VIN

VOUT

CIN

COUT

SW2

SW1

RSENSE

3774 F14

BOLD LINES INDICATE HIGH, SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH

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