LTC4449 datasheet(26/38 Pages) LINER

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LTC3774

3774fc

For more information www.linear.com/LTC3774

APPLICATIONS INFORMATION

INTVCC (LDO)

The LTC3774 features a true PMOS LDO that supplies

power to INTVCC from the VIN supply. INTVCC powers

the LTC3774’s internal circuitry. The LDO regulates the

voltage at the INTVCC pin to 5.5V when VIN is greater than

6V. The LDO can supply a peak current of 20mA and must

be bypassed to ground with a minimum of 4.7µF ceramic

capacitororlowESRelectrolyticcapacitor.Nomatterwhat

type of bulk capacitor is used, an additional 0.1µF ceramic

capacitor placed directly adjacent to the INTVCC and GND

pins is highly recommended.

For applications where the main input power is 5V, tie

the VIN and INTVCC pins together and tie the combined

pins to the 5V input with a 1Ω or 2.2Ω resistor as shown

in Figure 11 to minimize the voltage drop caused by the

gate charge current. This will override the INTVCC linear

regulator and will prevent INTVCC from dropping too low

due to the dropout voltage.

on-timetON(MIN)oftheLTC3774(≈90nswithpowerstage),

the input voltage and inductor value:

∆IL(SC) = tON(MIN) •

VIN

The resulting short-circuit current is:

ISC =

1/ 3VSENSE(MAX)

RSENSE

−

∆IL(SC)

⎛

⎝

⎜

⎞

⎠

⎟

After a short, or while starting, make sure that the load

current takes the folded-back current limit into account.

Phase-Locked Loop and Frequency Synchronization

The LTC3774 has a phase-locked loop (PLL) comprised

of an internal voltage-controlled oscillator (VCO) and a

phase detector. This allows the turn-on of the top MOSFET

to be locked to the rising edge of an external clock signal

applied to the MODE/PLLIN pin. The phase detector is

an edge sensitive digital type that provides zero degrees

phase shift between the external and internal oscillators.

This type of phase detector does not exhibit false lock to

harmonics of the external clock.

The output of the phase detector is a pair of complemen-

tary current sources that charge or discharge the internal

filter network. There is a precision 20µA current flowing

out of the FREQ pin. This allows the user to use a single

resistor to GND to set the switching frequency when no

external clock is applied to the MODE/PLLIN pin. The

internal switch between the FREQ pin and the integrated

PLL filter network is on, allowing the filter network to be

pre-charged at the same voltage as of the FREQ pin. The

relationship between the voltage on the FREQ pin and

operating frequency is shown in Figure 12 and specified

in the Electrical Characteristics table. If an external clock

is detected on the MODE/PLLIN pin, the internal switch

mentioned above turns off and isolates the influence of the

FREQpin.NotethattheLTC3774canonlybesynchronized

to an external clock whose frequency is within range of

the LTC3774’s internal VCO. A simplified block diagram

is shown in Figure 13.

Figure 11. Setup for a 5V Input

RVIN

1Ω

CIN

3774 F11

CINTVCC

4.7µF

INTVCC

LTC3774

VIN

Fault Conditions: Current Limit and Current Foldback

The LTC3774 includes current foldback to help limit

load current when the output is shorted to ground. If the

output falls below 50% of its nominal output level, then

the maximum sense voltage is progressively lowered

from its maximum programmed value to one-third of the

maximum value. Foldback current limiting is not disabled

during soft-start or tracking up. Under short-circuit condi-

tions with very low duty cycles, the LTC3774 will begin

cycle skipping in order to limit the short-circuit current.

In this situation the bottom MOSFET will be dissipating

most of the power but less than in normal operation. The

short circuit ripple current is determined by the minimum

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