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ADAU1977WBCPZ-R7 Datenblatt(PDF) 28 Page - Analog Devices

Teilenummer ADAU1977WBCPZ-R7
Bauteilbeschribung  Quad ADC with Diagnostics
PDF  68 Pages
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADAU1977WBCPZ-R7 Datenblatt(HTML) 28 Page - Analog Devices

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ADAU1977
Data Sheet
Rev. C | Page 28 of 68
The bit clock frequency depends on the sample rate, the slot
width, and the number of bit clocks per slot. Table 19 can be
used to calculate the BCLK frequency.
The sample rate (fS) can range from 8 kHz up to 192 kHz.
However, in master mode, the maximum bit clock frequency
(BCLK) is 24.576 MHz. For example, for a sample rate of
192 kHz, 128 × fS is the maximum possible BCLK frequency.
Therefore, only 128 bit clock cycles are available per TDM
frame. There are two options in this case: either operate with a
32-bit data width in TDM4 or operate with a 16-bit data width
in TDM8. In slave mode, this limitation does not exist because
the bit clock and frame clock are fed to the ADAU1977. Various
combinations of BCLK frequency and mode are available, but
care must be taken to choose the combination that is most
suitable for the application.
Connection Options
Figure 30 through Figure 34 show the available options for
connecting the serial audio port in I2S or TDM mode. In TDM
mode, it is recommended to include the pull-down resistor on
the data signal to prevent the line from floating when the
SDATAOUTx pin of ADAU1977 goes high-Z during an inactive
period. The resistor value should be such that no more than
2 mA is drawn from the SDATAOUTx pin. Although the resistor
value is typically in the range of 10 kΩ to 47 kΩ, the appropriate
resistor value depends on the devices on the data bus.
Table 19. Bit Clock Frequency TDM Mode
BCLK Frequency
Mode
16 Bit Clocks Per Slot
24 Bit Clocks Per Slot
32 Bit Clocks Per Slot
TDM2
32 × fS
48 × fS
64 × fS
TDM4
64 × fS
96 × fS
128 × fS
TDM8
128 × fS
192 × fS
256 × fS
TDM16
256 × fS
384 × fS
512 × fS
Figure 30. Serial Port Connection Option 1—I2S/LJ/RJ Mode, ADAU1977 Master
Figure 31. Serial Port Connection Option 2—I2S/LJ/RJ Mode, ADAU1977 Slave
DSP
SLAVE
MASTER
ADAU1977
BCLK
LRCLK
SDATAOUT1
SDATAOUT2
DSP
MASTER
SLAVE
ADAU1977
BCLK
LRCLK
SDATAOUT1
SDATAOUT2



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