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ADAU1977WBCPZ-R7 Datenblatt(PDF) 41 Page - Analog Devices |
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ADAU1977WBCPZ-R7 Datenblatt(HTML) 41 Page - Analog Devices |
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41 / 68 page ![]() Data Sheet ADAU1977 Rev. C | Page 41 of 68 Bits Bit Name Settings Description Reset Access 0 BOOST_RCVR Boost Recovery Mode. 0x1 RW 0 Automatic Fault Recovery 1 Manual Fault Recovery; Use MRCV to Recover BLOCK POWER CONTROL AND SERIAL PORT CONTROL REGISTER Address: 0x04, Reset: 0x3F, Name: BLOCK_POWER_SAI Table 30. Bit Descriptions for BLOCK_POWER_SAI Bits Bit Name Settings Description Reset Access 7 LR_POL Sets LRCLK Polarity. 0x0 RW 0 LRCLK Low then High 1 LRCLK High then Low 6 BCLKEDGE Sets the Bit Clock Edge on Which Data Changes. 0x0 RW 0 Data Changes on Falling Edge 1 Data Changes on Rising Edge 5 LDO_EN LDO Regulator Enable. 0x1 RW 0 LDO Powered Down 1 LDO Enabled 4 VREF_EN Voltage Reference Enable. 0x1 RW 0 Voltage Reference Powered Down 1 Voltage Reference Enabled 3 ADC_EN4 ADC Channel 3 Enable. 0x1 RW 0 ADC Channel Powered Down 1 ADC Channel Enabled 2 ADC_EN3 ADC Channel 3 Enable. 0x1 RW 0 ADC Channel Powered Down 1 ADC Channel Enabled 1 ADC_EN2 ADC Channel 2 Enable. 0x1 RW 0 ADC Channel Powered Down 1 ADC Channel Enabled 0 ADC_EN1 ADC Channel 1 Enable. 0x1 RW 0 ADC Channel Powered Down 1 ADC Channel Enabled |
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