 |
Datenblatt-Suchmaschine für elektronische Bauteile |
|
|
Datenblatt-Suchmaschine für elektronische Bauteile |
|
ADAU1977WBCPZ-R7 Datenblatt(PDF) 16 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADAU1977WBCPZ-R7 Datenblatt(HTML) 16 Page - Analog Devices |
|
|
16 / 68 page  ADAU1977 Data Sheet Rev. C | Page 16 of 68 Depending on CEXT, tD may vary and in turn decide the minimum hold period for the RST pulse. The RST pulse must be held low for the tD time period to initialize the core properly. The required RST low pulse period can be reduced by adding a resistor across CEXT. The new tD value can then be calculated as tD = 1.32 × REQ × CEXT where REQ = 64 kΩ || REXT. The resistor ensures that DVDD not only discharges quickly during a reset or an AVDDx power loss but also resets the internal blocks correctly. Note that some power loss in this resistor is to be expected because the resistor constantly draws current from DVDD. The typical value for CEXT is 10 µF and for REXT is 3 kΩ. This results in a time constant of tD = 1.32 × REQ × CEXT = 37.8 ms where REQ = 2.866 kΩ (64 kΩ || 3 kΩ). Using this equation at a set CEXT value, the REXT can be calculated for a desired RST pulse period. There is also a software reset register (S_RST, Bit 7 of Register 0x00) available that can be used to reset the part, but it must be noted that during an AVDDx power loss, the software reset may not ensure proper initialization because DVDD may not be stable. Figure 14. DVDD Regulator Output Connections PLL AND CLOCK The ADAU1977 has a built-in analog PLL to provide a jitter- free master clock to the internal ADC. The PLL must be programmed for the appropriate input clock frequency. The PLL Control Register 0x01 is used for setting the PLL. The CLK_S bit (Bit 4) of Register 0x01 is used for setting the clock source for the PLL. The clock source can be either the MCLKIN pin or the LRCLK pin (slave mode). In LRCLK mode, the PLL can support sample rates between 32 kHz and 192 kHz. In MCLK input mode, the MCS bits (Bits[2:0] of Register 0x01) must be set to the desired input clock frequency for the MCLKIN pin. Table 10 shows the input MCLK required for the most common sample rates and the MCS bit settings. The PLL_LOCK bit (Bit 7) of Register 0x01 indicates the lock status of the PLL. It is recommended that after initial power-up the PLL lock status be read to ensure that the PLL outputs the correct frequency before unmuting the audio outputs. Table 10. Required Input MCLK for Common Sample Rates MCS (Bits[2:0]) fS (kHz) Frequency Multi- plication Ratio MCLKIN Frequency (MHz) 000 32 128 × fS 4.096 001 32 256 × fS 8.192 010 32 384 × fS 12.288 011 32 512 × fS 16.384 100 32 768 × fS 24.576 000 44.1 128 × fS 5.6448 001 44.1 256 × fS 11.2896 010 44.1 384 × fS 16.9344 011 44.1 512 × fS 22.5792 100 44.1 768 × fS 33.8688 000 48 128 × fS 6.144 001 48 256 × fS 12.288 010 48 384 × fS 18.432 011 48 512 × fS 24.576 100 48 768 × fS 36.864 000 96 64 × fS 6.144 001 96 128 × fS 12.288 010 96 192 × fS 18.432 011 96 256 × fS 24.576 100 96 384 × fS 36.864 000 192 32 × fS 6.144 001 192 64 × fS 12.288 010 192 96 × fS 18.432 011 192 128 × fS 24.576 100 192 192 × fS 36.864 The PLL can accept the audio frame clock (sample rate clock) as input, but the serial port must be configured as a slave and the frame clock must be fed to the part from the master. It is strongly recommended that the PLL be disabled, reprogrammed with the new setting, and then reenabled. A lock bit is provided that can be polled via the I2C to check whether the PLL has acquired lock. The PLL requires an external filter, which is connected at the PLL_FILT pin (Pin 3). The recommended PLL filter circuit for MCLK or LRCLK mode is shown in Figure 15. Using NPO capacitors is recommended for temperature stability. Place the filter components close to the device for best performance. Figure 15. PLL Filter 3.3V TO 1.8V REGULATOR DVDD ADAU1977 IOVDD +1.8V OR +3.3V C 0.1µF C 0.1µF CEXT 10µF MLCC X7R REXT 3kΩ AVDD1 AVDD3 AVDD2 +3.3V TO INTERNAL BLOCKS AVDDx PLL_LF LRCLK MODE 39nF 4.87kΩ 2.2nF AVDDx PLL_LF MCLK MODE 5.6nF 1kΩ 390pF |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
German ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
