AD9136-EBZ datasheet(44/117 Pages) AD

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AD9135/AD9136

Data Sheet

Rev. C | Page 44 of 117

Sync Procedure

The procedure for enabling the sync is as follows:

Set Register 0x008 to 0x03 to sync the LMFC for both

DAC0 and DAC1.

Set the desired sync processing mode. The sync processing

mode settings are listed in Table 41.

For Subclass 1, set the error window according to the

uncertainty of the SYSREF signal relative to the DAC clock

and the tolerance of the application for deterministic

latency uncertainty. Sync window tolerance settings are

given in Table 42.

Enable sync by writing 1 to SYNCENABLE

(Register 0x03A[7]).

If in one-shot mode, arm the sync machine by writing 1 to

SYNCARM (Register 0x03A[6]).

If in Subclass 1, ensure that at least one SYSREF± pulse is

sent to the device.

Check the status by reading the following bit fields:

SYNC_BUSY (Register 0x03B[7]) = 0 to indicate that

the sync logic is no longer busy.

SYNC_LOCK (Register 0x03B[3]) = 1 to indicate that

the signals are aligned. This bit updates on every

phase check.

SYNC_WLIM (Register 0x03B[1]) = 0 to indicate that

the phase error is not beyond the specified error

window. This bit updates on every phase check.

SYNC_ROTATE (Register 0x03B[2]) = 1. If the phases

were not aligned before the sync and an alignment

occurred, this bit indicates that a clock alignment

occurred. This bit is sticky and can be cleared only by

writing to the SYNCCLRSTKY control bit

(Register 0x03A[5]).

SYNC_TRIP (Register 0x03B[0]) = 1 to indicate that

the alignment edge was received and a phase check

occurred. This bit is sticky and can be cleared only by

writing to the SYNCCLRSTKY control bit

(Register 0x03A[5]).

Table 41. Sync Processing Modes

Sync Processing Mode

SYNCMODE (Register 0x03A[3:0])

One-shot

0x01

Continuous

0x02

One-shot then monitor

0x09

Table 42. Sync Window Tolerance

Sync Error Window

Tolerance

ERRWINDOW (Register 0x034[2:0])

±½ DAC clock cycles

0x00

±1 DAC clock cycles

0x01

±2 DAC clock cycles

0x02

±3 DAC clock cycles

0x03

LMFC Sync IRQ

The sync status bits (SYNC_LOCK, SYNC_ROTATE,

SYNC_TRIP, and SYNC_WLIM) are available as IRQ events.

Use Register 0x021[3:0] to enable the sync status bits for DAC0

and then use Register 0x025[3:0] to read back their statuses and

to reset the IRQ signals.

Use Register 0x022[3:0] to enable the sync status bits for DAC1

and then use Register 0x026[3:0] to read back their statuses and

to reset the IRQ signals.

See the Interrupt Request Operation section for more information.

Deterministic Latency

JESD204B systems contain various clock domains distributed

throughout each system. Data traversing from one clock

domain to a different clock domain can lead to ambiguous

delays in the JESD204B link. These ambiguities lead to

nonrepeatable latencies across the link from power cycle to

power cycle with each new link establishment. Section 6 of the

JESD204B specification addresses the issue of deterministic

latency with mechanisms defined as Subclass 1 and Subclass 2.

The AD9135/AD9136 support JESD204B Subclass 0 and

Subclass 1 operation, but not Subclass 2. Write the subclass to

Subclass 0

This mode does not require any signal on the SYSREF± pins,

which can be left disconnected.

Subclass 0 still requires that all lanes arrive within the same LMFC

cycle and that the two DACs be synchronized to each other.

Minor Subclass 0 Caveats

Because the AD9135/AD9136 require an ILAS, the nonmultiple

converter device alignment single lane (NMCDA-SL) case from

the JESD204A specification is supported only when using the

optional ILAS.

Error reporting using SYNCOUTx± is not supported when

using Subclass 0 with F = 1.

Subclass 1

This mode gives deterministic latency and allows links to be

synced to within ½ of a DAC clock period. It requires an

external SYSREF± signal that is accurately phase aligned to the

DAC clock.

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