AD9136-EBZ datasheet(2/117 Pages) AD

2 / 117 page

AD9135/AD9136

Data Sheet

Rev. C | Page 2 of 117

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Typical Application Circuit ............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

DC Specifications ......................................................................... 5

Digital Specifications ................................................................... 6

Maximum DAC Update Rate Speed Specifications by Supply7

JESD204B Serial Interface Speed Specifications ...................... 7

SYSREF Signal to DAC Clock Timing Specifications.............. 8

Digital Input Data Timing Specifications ................................. 8

Latency Variation Specifications ................................................ 9

JESD204B Interface Electrical Specifications ........................... 9

AC Specifications........................................................................ 10

Absolute Maximum Ratings.......................................................... 11

Thermal Resistance .................................................................... 11

ESD Caution................................................................................ 11

Pin Configuration and Function Descriptions........................... 12

Terminology .................................................................................... 15

Typical Performance Characteristics ........................................... 16

Theory of Operation ...................................................................... 22

Serial Port Operation ..................................................................... 23

Data Format ................................................................................ 23

Serial Port Pin Descriptions...................................................... 23

Serial Port Options ..................................................................... 23

Chip Information............................................................................ 25

Device Setup Guide ........................................................................ 26

Overview...................................................................................... 26

Step 1: Start Up the DAC ........................................................... 26

Step 2: Digital Datapath............................................................. 27

Step 3: Transport Layer.............................................................. 27

Step 4: Physical Layer................................................................. 28

Step 5: Data Link Layer.............................................................. 28

Step 6: Optional Error Monitoring .......................................... 29

Step 7: Optional Features........................................................... 29

DAC PLL Setup........................................................................... 30

Interpolation ............................................................................... 30

JESD204B Setup ......................................................................... 30

SERDES Clocks Setup................................................................ 32

Equalization Mode Setup .......................................................... 32

Link Latency Setup..................................................................... 32

Crossbar Setup............................................................................ 34

JESD204B Serial Data Interface.................................................... 35

JESD204B Overview .................................................................. 35

Physical Layer ............................................................................. 36

Data Link Layer .......................................................................... 39

Transport Layer .......................................................................... 48

JESD204B Test Modes ............................................................... 58

JESD204B Error Monitoring..................................................... 59

Hardware Considerations ......................................................... 61

Digital Datapath ............................................................................. 65

DAC Paging................................................................................. 65

Data Format ................................................................................ 65

Interpolation Filters ................................................................... 65

Inverse Sinc ................................................................................. 66

Digital Gain, DC Offset, and Group Delay............................. 66

Downstream Protection ............................................................ 68

Datapath PRBS ........................................................................... 69

DC Test Mode ............................................................................. 70

Interrupt Request Operation ........................................................ 71

Interrupt Service Routine.......................................................... 71

DAC Input Clock Configurations ................................................ 72

Driving the CLK± Inputs .......................................................... 72

DAC PLL Fixed Register Writes ............................................... 72

Clock Multiplication .................................................................. 72

Starting the PLL.......................................................................... 74

Analog Outputs............................................................................... 75

Transmit DAC Operation.......................................................... 75

Device Power Dissipation.............................................................. 78

Temperature Sensor ................................................................... 78

Start-Up Sequence.......................................................................... 79

Step 1: Start Up the DAC........................................................... 79

Step 2: Digital Datapath............................................................. 79

Step 3: Transport Layer.............................................................. 80

Step 4: Physical Layer................................................................. 80

Step 5: Data Link Layer.............................................................. 81

Step 6: Error Monitoring ........................................................... 81

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