AD9136-EBZ datasheet(58/117 Pages) AD

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AD9135/AD9136

Data Sheet

Rev. C | Page 58 of 117

JESD204B TEST MODES

PHY PRBS Testing

The JESD204B receiver on the AD9135/AD9136 includes a

PRBS pattern checker on the back end of its physical layer.

This functionality enables bit error rate (BER) testing of each

physical lane of the JESD204B link. The PHY PRBS pattern

checker does not require that the JESD204B link be established.

The pattern checker can synchronize with a PRBS7, PRBS15,

or PRBS31 data pattern. PRBS pattern verification can be

performed on multiple lanes at once. The error counts for

failing lanes are reported for one JESD204B lane at a time. The

process for performing PRBS testing on the AD9135/AD9136 is

as follows:

Start sending a PRBS7, PRBS15, or PRBS31 pattern from

the JESD204B transmitter.

Select and write the appropriate PRBS pattern to

Enable the PHY test for all lanes being tested by writing to

PHY_TEST_EN (Register 0x315). Each bit of Register 0x315

enables the PRBS test for the corresponding lane. For example,

writing a 1 to Bit 0 enables the PRBS test for Physical Lane 0.

Toggle PHY_TEST_RESET (Register 0x316[0]) from 0 to 1

then back to 0.

Set PHY_PRBS_ERROR_THRESHOLD (Register 0x317 to

Write a 0 and then a 1 to PHY_TEST_START

(Register 0x316[1]). The rising edge of PHY_TEST_START

starts the test.

Wait 500 ms.

Stop the test by writing PHY_TEST_START

(Register 0x316[1]) = 0.

Read the PRBS test results.

Each bit of PHY_PRBS_PASS (Register 0x31D)

corresponds to one SERDES lane: 0 is fail, 1 is pass.

The number of PRBS errors seen on each failing lane

can be read by writing the lane number to check (0 to 7)

in the PHY_SRC_ERR_CNT (Register 0x316[6:4]) and

reading the PHY_PRBS_ERR_CNT (Register 0x31A

to Register 0x31C). The maximum error count is 224 − 1.

If all bits of Register 0x31A to Register 0x31C are high,

the maximum error count on the selected lane has

been exceeded.

Table 54. PHY PRBS Pattern Selection

PHY_PRBS_PAT_SEL Setting,

(Register 0x316[3:2])

PRBS Pattern

0b00 (default)

PRBS7

0b01

PRBS15

0b10

PRBS31

Transport Layer Testing

The JESD204B receiver in the AD9135/AD9136 supports the

short transport layer (STPL) test as described in the JESD204B

standard. This test can be used to verify the data mapping

between the JESD204B transmitter and receiver. To perform

this test, this function must be implemented in the logic device

and enabled there. Before running the test on the receiver side,

the link must be established and running without errors (see the

Device Setup Guide).

The STPL test ensures that each sample from each converter is

mapped appropriately according to the number of converters

(M) and the number of samples per converter (S). As specified

in the JESD204B standard, the converter manufacturer specifies

what test samples are transmitted. Each sample must have a

unique value. For example, if M = 2 and S = 2, there are 4

unique samples transmitted repeatedly until the test is stopped.

The expected sample must be programmed into the device and

the expected sample is compared to the received sample one

sample at a time until all have been tested. The process to

perform this test on the AD9135/AD9136 is described as follows:

Synchronize JESD204B link.

Enable the STPL test at the JESD204B transmitter.

Select Converter 0 Sample 0 for testing. Write

SHORT_TPL_DAC_SEL (Register 0x32C[3:2]) = 0 and

SHORT_TPL_SP_SEL (Register 0x32C[5:4]) = 0.

Set the expected test sample for Converter 0, Sample 0.

Program the expected 11-/16-bit test sample into the

SHORT_TPL_REF_SP_x registers (Register 0x32E and

Enable the STPL test. Write SHORT_TPL_TEST_EN

(Register 0x32C[0]) = 1.

Toggle the STPL reset. SHORT_TPL_TEST_RESET

(Register 0x32C[1]) from 0 to 1 then back to 0.

Check for failures. Read SHORT_TPL_FAIL

(Register 0x32F[0]): 0 is pass, 1 is fail.

Repeat Step 3 to Step 7 for each sample of each converter,

Conv0Sample0 through ConvM − 1SampleS − 1.

Repeated CGS and ILAS Test

As per Section 5.3.3.8.2 of the JESD204B specification, the

AD9135/AD9136 can check that a constant stream of /K28.5/

characters is being received, or that CGS followed by a constant

stream of ILAS is being received.

To run a repeated CGS test, send a constant stream of /K28.5/

characters to the AD9135/AD9136 SERDES inputs. Next, set up

the device and enable the links as described in the Device Setup

Guide section. Ensure that the /K28.5/ characters are being

received by verifying that the SYNCOUTx± has been deasserted

and that CGS has passed for all enabled link lanes by reading

status of lanes on Link 0, and Register 0x300[2] = 1 to monitor

the status of lanes on Link 1 for dual-link mode.

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