ELD5016 datasheet(20/38 Pages) EMC

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eLD5016

8-Bit Microcontroller



Product Specification (V1.0) 2.16.2017

(This specification is subject to change without prior notice)

5.2 Special Function Registers

5.2.1 A (Accumulator)

Internal data transfer operation, or instruction operand holding usually involves the

temporary storage function of the Accumulator, which is not an addressable register.

5.2.2 CONT (Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INT_EDGE

INT

PAB

PSR2

PSR1

PSR0

R/W-0

R-0

R/W-0

The CONT register is both readable and writable by instruction

“CONTW” and

“CONTR”.

Bit 7 (INT_EDGE): interrupt edge type of P70

0: P70's interrupt sources are rising and falling edge signals.

1: P70's interrupt source is a falling edge signal.

Bit 6 (INT):

Interrupt Enable flag

0: Masked by DISI or hardware interrupt

1: Enabled by ENI / RETI instructions

Bit 5 (TS):

TCC signal source

0: Instruction clock

1: 16384 Hz

Instruction clock = MCU clock / 2. Refer to RA Bits 4 ~ 6 for PLL and

Main clock selection. See Figure 5-5 for details.

Bit 4:

Undefined bits, set to

“0” at all time

Bit 3 (PAB): Prescaler Assignment Bit

0: TCC

1: WDT

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