ELD5016 datasheet(10/38 Pages) EMC

10 / 38 page

eLD5016

8-Bit Microcontroller



Product Specification (V1.0) 2.16.2017

(This specification is subject to change without prior notice)



The configuration structure generates 16k

 13 bits on-chip ROM addresses to the

relative programming instruction codes. One program page is 1024 words long.



R2 is set as all "0" under RESET condition.



"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,

"JMP" allows the PC to go to any location within a page.



"CALL" instruction loads the lower 10 bits of the PC, and then PC + 1 are pushed

onto the stack. Thus, the subroutine entry address can be located anywhere within

a page.



"RET" ("RETL k", "RETI") instruction loads the program counter with the contents

of the top-level stack.



Any instruction written to R2 (e.g.,

“ADD R2, A”, "MOV R2, A", "BC R2,6", etc.) will

cause the 9th and the 10th bits (A8 ~ A9) of the PC to be cleared. Hence, the

computed jump is limited to the first 256 locations of a page.



"TBL" allows a relative address to be added to the current PC while contents of the

9th and the 10th bits remain unchanged. The most significant bits (A10 ~ A13) will be

loaded with the content of bit PS0 ~ PS3 in the status register (R5) upon the

execution of a "JMP", "CALL", "ADD R2, A'', or "MOV R2, A'' instruction.



The Data Memory Configuration is as follows:

R PAGE Registers

IOC PAGE

Addr

R PAGE0

R PAGE1

IOC PAGE0

IOC PAGE1

INDA

Indirect addressing

TCCD

TCC data

Program counter

STA

IOC Page, Status

RBSR

P5IOD

CDAD

P5IOC

CDAC

Port 5 I/O data, Program

page

Current DAC

input data

Port 5 I/O

control,

(P76, P77)

open drain

Clear CDA, ASPCM rate

and volume control

P6IOD

P6IOC

Port 6 I/O data

Port 6 I/O

control

(undefined, non-existent

and set to

“0” at all time)

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