ELD5016 datasheet(9/38 Pages) EMC

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eLD5016

8-Bit Microcontroller

Product Specification (V1.0) 2.16.2017

 5

(This specification is subject to change without prior notice)

5.1 Operational Registers

5.1.1 R0 (IndA: Indirect Addressing Register)

R0 is not a physically implemented register. It is useful as an indirect addressing

pointer. Any instruction using R0 as register actually accesses data pointed by the

RAM Select Register (R4).

Example:

MOV

A, @0x20

; store an address at R4 for indirect addressing

MOV

0x04, A

MOV

A, @0xAA

; write data 0xAA to R20 at Bank0 through R0

MOV

0x00, A

5.1.2 R1 (TCCD: TCC Data)



Increased by the instruction cycle clock.



Writable and readable by the program as any other register.



Defined by PAB (CONT-3) reset.



The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.



The contents of the prescaler counter will be cleared only when the TCC register is

written with a value.

5.1.3 R2 (PC: Program Counter and Stack)



Depending on the device type, R2 and hardware stack are 10-bit wide. The

structure is depicted in the following figure.

A13 A12 A11 A10

A9 A8

A7~A0

0000

PAGE0 0000~03FF

0001

PAGE1 0400~07FF

1111 PAGE15 3C00~3FFF

0010

PAGE2 0800~0BFF

Stack 1

Stack 2

Stack 3

Stack 4

Stack 5

Stack 6

Stack 7

Stack 8

CALL

RET

RETL

RETI

1110 PAGE14 3800~3BFF

Figure 5-3 Program Counter Organization

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