SB710 datasheet(37/88 Pages) AMD

37 / 88 page

45215

Rev. 1.60 November 09

AMD SB710 Databook

Signal Description

Pin Name

Type

Voltage

Functional Description

SLP_S3#

S5_3.3V

S3 Sleep Power plane control

Assertion of SLP_S3# shuts off power to non-critical components

when system transitions to S3, S4, or S5 states. Assertion takes

place sometime after CPU_STP# is asserted.

De-assertion of SLP_S3# turns on power to non-critical components

when system transitions from S3, S4, or S5 back to S0. De-

assertion takes place sometime after a wake-up event has been

triggered.

SLP_S5#

S5_3.3V

S5 Sleep Power plane control -

Assertion of SLP_S5# shuts power off to non-critical components

when system transitions to S4 or S5 state. Assertion takes place

sometime after CPU_STP# is asserted.

De-assertion of SLP_S5# turns on power to non-critical components

when transitioning from S4/S5 back to S0 state. De-assertion takes

place sometime after a wake-up event is triggered.

SMBALERT#/

THRMTRIP#/

GEVENT2#

I/O

S5_3.3V

SMBus Alert / Thermal Trip / General Event 2

Thermal Trip: Signal indicates to the SB710 that a thermal trip has

occurred. Its assertion will cause the SB710 to transition the system

to S5 immediately, without waiting for the STPGNT message from

the processor.

SUS_STAT#

S5_3.3V

Suspend Status -

Assertion by the SB710 indicates that the system will be entering a

low-power state soon. The signal is monitored by those devices with

memory that needs to switch from normal refresh to suspend

refresh mode when the system transitions to a low-power state.

Assertion takes place after the Stop Grant message from the CPU is

received by the system.

De-assertion by the SB710 indicates that the system is exiting a low

power state now and is returning to S0

. De-assertion takes place

after LDT_STP# is de-asserted.

TEMPIN3/

TALERT#/

GPIO64

I/O

S5_3.3V

Temperature Monitor Input 3/ Thermal Alert / GPIO 64

Thermal Alert: The signal is a thermal alert to the SB710. SB710

can be programmed to generate an SMI#, SCI, or IRQ13 through

GPE, or generate an SMI# without GPE in response to the signal’s

assertion. See the AMD SB700/SB710/SB750 Register Reference

Guide

for details.

S3_STATE/

GEVENT5#

I/O

S5_3.3V

S3 State: Assertion of S3_STATE by the SB710 indicates to the

power supply that the system has transitioned into S3 state.

Asserted after the Sleep S3 command is completed. De-assertion

indicates that the system is leaving S3 state. De-assertion takes

place after SUS_STAT# is de-asserted.

SB710 Datenblatt(PDF) 37 Page - Advanced Micro Devices

SB710 Datenblatt(HTML) 37 Page - Advanced Micro Devices

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