SB710 datasheet(46/88 Pages) AMD

46 / 88 page

AMD SB710 Databook

45215 Rev. 1.60 November 09

Signal Description

7.17

Reset / Clocks / ATE

Note: Clock generator function is NOT SUPPORTED by the SB710.

Pin Name

Type

Voltage

Functional Description

A_RST#

S5_3.3V

PCI Host Bus Reset. Asserted during transition to S3/S4/S5

to reset all devices in the SB710 or connected to it, except

the ACPI logic in the SB710

14M_X1

AVDDCK_1.2

Reserved. See the AMD SB700/SB710/SB750 Schematic

Review Checklist

for how to connect.

14M_X2

AVDDCK_1.2

Reserved. See the AMD SB700/SB710/SB750 Schematic

Review Checklist

for how to connect.

PCIE_RCLKP/

NB_LNK_CLKP

I/O

CKVDD_1.2

Positive phase 100-MHz reference clock (positive) for

SB710.

PCIE_RCLKN/

NB_LNK_CLKN

I/O

CKVDD_1.2

Negative phase 100-MHz reference clock (negative) for

SB710.

GPP_CLK[3:0]P

CKVDD_1.2

Reserved. See the AMD SB700/SB710/SB750 Schematic

Review Checklist

for how to connect.

GPP_CLK[3:0]N

CKVDD_1.2

Reserved. See the AMD SB700/SB710/SB750 Schematic

Review Checklist

for how to connect.

CLK_REQ0#/SATA_IS3#/

GPIO0

3.3 V

PCI-E clock request 0

CLK_REQ1#/SATA_IS4#/

FANOUT3/GPIO39

3.3 V

PCI-E clock request 1

CLK_REQ2#/SATA_IS5#/

FANIN3/GPIO40

3.3 V

PCI-E clock request 2

CLK_REQ3#/SATA_IS1#/

GPIO6

3.3 V

PCI-E clock request 3

25M_48M_66M_OSC

S5_VDD33

14 MHz reference clock input

NB_DISP_CLKP

CKVDD_1.2

Reserved. See the AMD SB700/SB710/SB750 Schematic

Review Checklist

for how to connect.

NB_DISP_CLKN

CKVDD_1.2

Reserved. See the AMD SB700/SB710/SB750 Schematic

Review Checklist

for how to connect.

CPU_HT_CLKP

CKVDD_1.2

Reserved. See the AMD SB700/SB710/SB750 Schematic

Review Checklist

for how to connect.

CPU_HT_CLKN

CKVDD_1.2

Reserved. See the AMD SB700/SB710/SB750 Schematic

Review Checklist

for how to connect.

NB_HT_CLKP

CKVDD_1.2

Reserved. See the AMD SB700/SB710/SB750 Schematic

Review Checklist

for how to connect.

NB_HT_CLKN

CKVDD_1.2

Reserved. See the AMD SB700/SB710/SB750 Schematic

Review Checklist

for how to connect.

SLT_GFX_CLKP

CKVDD_1.2

Reserved. See the AMD SB700/SB710/SB750 Schematic

Review Checklist

for how to connect.

SLT_GFX_CLKN

CKVDD_1.2

Reserved. See the AMD SB700/SB710/SB750 Schematic

Review Checklist

for how to connect.

USBCLK/

14M_25M_48M_OSC

I/O

S5_3.3V

48-MHz input clock used for USB

SB710 Datenblatt(PDF) 46 Page - Advanced Micro Devices

SB710 Datenblatt(HTML) 46 Page - Advanced Micro Devices

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