SB710 datasheet(13/88 Pages) AMD

13 / 88 page

45215

Rev. 1.60 November 09

AMD SB710 Databook

SB710 Power on Sequence and Timing

3 SB710 Power on Sequence and Timing

3.1

Power Up and Down Sequences

Simple diagrams of the SB710 power up sequences are shown in Figure 3-1 and Figure 3-2 below. A

power detection circuit is integrated into the SB710. This circuit will monitor SB PWR_GOOD and will

assert A_RST# and LDT_RST# for as long as SB PWR_GOOD is false. After SB PWR_GOOD has been

asserted, A_RST#, followed by LDT_RST#, will be de-asserted. Table 4-1 shows the timing requirements

referenced in Figure 3-1 through Figure 3-5. Besides the illustrated requirements, it is also required that

the ramp time for any rail be less than 40ms.

Table 3-1: SB710 Power Up/Down Sequence Timing

Symbol

Min.

Max.

Description

Note 1

+3.3V_S5 to +1.2V_S5

10 ms

–

+3.3V_S5 to resume reset (RSMRST#).

T2A

–

50 ms

Resume reset (RSMRST#) rise time (10% to 90%). SB710 has a Schmitt trigger

input with de-bouncing logic on this pin, so the value is relaxed relative to earlier

AMD SB designs.

32 ms

–

RSMRST# de-asserted to Start of RTCCLK output from SB710.

50 ns

SB PWR_GOOD de-assertion to NB_PWRGD de-assertion delay.

0 ns

30 ns

SB PWR_GOOD assertion to NB_PWRGD assertion delay when using the

SB710 NB_PWRGD output. This parameter is the internal delay of the SB. The

system board design may add additional delay due to loading and trace length.

The acceptable delay including system layout / loading is 1 ms maximum..

T7A

–

50 ms

SB PWR_GOOD rise time (10% to 90 %). See Note 3. SB710 has a Schmitt

trigger with de-bouncing logic on this pin, so the value is relaxed relative to

earlier AMD SB designs.

T7B

–

1 ms

SB PWR_GOOD fall time.

0 ns

T8A

Note 4

100 ns

A_RST# (PCI host bus reset) to PCIRST#.

T8B

–

Note 5

KBRST# to A_RST#.

T8C

1.0 ms

2.3 ms

PCIRST# to LDT_RST#.

T8D

98 ms

108 ms

NB_PWRGD to LDT_PG.

101 ms

113 ms

SB PWR_GOOD to PCIRST#.

T9A

101 ms

113 ms

SB PWR_GOOD to A_RST# (T9-T8A).

T9B

31 ms

–

SB PWR_GOOD to LDT_STP#. See Note 11

T10

-31 ms

–

PCIE_CLKP/N stable time before SB PWRGOOD assertion.

T11

36 ms

41 ms

SB PWR_GOOD to stable PCICLK 33 MHz. See Note 8.

–

15 ns

Wake Event (except PwrButton) to SLP_S3# / SLP_S5#.

200 ns

–

Wake Event (PwrButton) to SLP_S3# / SLP_S5# (S5/S4/S3  S0)

T13

8 ns

Wake Event (PwrButton) to SLP_S3# / SLP_S5# (G3  S5  S0)

T13A

80 ns

–

SB PWR_GOOD must be de-asserted before VDD (PS PWOK) drops more than

5% off the nominal value. See Note 9.

T14

1 ns

–

SB PWR_GOOD de-assertion to Resume Reset (RSMRST#) assertion. See

Note 10.

T15

5 s

–

[Not illustrated] VBAT to +3.3V_S5 to +1.2V_S5. Must be greater than 5

seconds to allow start time for the internal RTC.

T16A

40 µs

–

LDT_STP# assertion to LDT_RST# assertion.

T16B

4 µs

–

LDT_RST# assertion to SLP_S3# assertion.

See Notes 1 to 12 in the Power Up Sequence Timing Notes section following the timing diagrams.

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