T15V2M08A datasheet(7/12 Pages) TMT

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Preliminary T15V2M08A

Taiwan Memory Technology, Inc. reserves the right

P. 7

Publication Date: MAR. 2001

to change products or specifications without notice.

Revision:0.A

TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled)

READ CYCLE 2

(Chip Enable Controlled)

Notes (READ CYCLE) :

1. WE are high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to

VOH or VOL levels.

4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device

and from device to device interconnection.

5. Transition is measured

±200mV from steady state voltage with load. This parameter is sampled and not

100% tested.

6. Device is continuously selected with

=VIL .

DON' T CARE

UNDEFINED

C E 1

OLZ

C E 2

AC E

OHZ

D OUT

tRC

A d d r e s s

tOH

tAA

D OUT

Previous Data Valid

Data Valid

T15V2M08A Datenblatt(PDF) 7 Page - Taiwan Memory Technology