TE

CH

tm

Preliminary T15V2M08A

Taiwan Memory Technology, Inc. reserves the right

P. 8

Publication Date: MAR. 2001

to change products or specifications without notice.

Revision:0.A

WRITE CYCLE 1

WRITE CYCLE 2

( CE Controlled)

NOTES ( WRITE CYCLE ) :

1. A write occurs during the overlap of a low

1

CE , a high CE2 and a low WE . A write begins at

the lateat transition among

1

CE goes low, CE2 going high and WE going low. A write end at the

earliest transition among

1

CE

going high, CE2 going low and WE going high. tWP is measured

from the beginning of write to the end of write.

2. tCW is measured from the later of

1

CE

going low or CE2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change.

tWC

tWHZ

tDW

D I N

tDH

tWR

tAS

tWP

A d d r e s s

C E 2

C E 1

W E

D O U T

tAW

t

CW

tOW

H ig h- Z

H i g h - Z

D O N ' T C A R E

U N D E F I N E D

tWC

tDW

D I N

tDH

tWR

tAS

tWP

tCW

A d d r e s s

C E 1

W E

D O U T

C E 2

tAW

H ig h - Z

H ig h - Z

H i g h - Z