VD6640 datasheet(75/126 Pages) STMICROELECTRONICS

75 / 126 page

DocID023597 Rev 11

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VG6640, VD6640

Video timing

125

Figure 21. Clock settings

The equations relating the input clock frequency to pixel clock frequencies are:

NOTE:

OP_Pix_Clk_Div must be kept at 8 for correct operation of CSI-2 interface.

The user must write the frequency of clock applied to the EXTCLK_XTAL1 input to

the register 0x0310, ExtClk_Frequency_MHz.

6.3.1

Spread spectrum

The PLL contains a spread spectrum clock generator (SSCG) block for the purposes of EMI

reduction. This feature is off by default and is intended for use if RF channel blocking

becomes an issue on the host system. The modulation period and depth are fully

programmable. The spread mode is selectable between center spread (default) or down

spread. The SSCG registers must only be reprogrammed with new values when the sensor

is in standby mode.

VT_PixelClock_MHz

ExtClk_Xtal1_MHz

PLL_Multiplier

Pre_PLL_Clk_Div

VT_Sys_Clk_Div

VT_Pix_Clk_Div

------------------------------------------------------------------------------------------------------------------------------------------------------------------

OpClock_MHz

ExtClk_Xtal1_MHz

PLL_Multiplier

Pre_PLL_Clk_Div

× P_Sys_Clk_Div OP_Pix_Clk_Div

--------------------------------------------------------------------------------------------------------------------------------------------------------------------

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