VD6640 datasheet(20/126 Pages) STMICROELECTRONICS

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Functional description

VG6640, VD6640

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DocID023597 Rev 11

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HDR video pipe

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Responsible for real-time image data processing at pixel clock rate. Processes the

raw pixel data from the ADCs in the CAB. The HDR video pipe contains a set of

correction algorithm blocks and dedicated blocks for data coding.

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Manages the 22bit to12bit compression using a programmable 32 element PWL

table.

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Image data transmitters

–

Video data coders and transmitters, including serial (MIPI) and parallel interfaces.

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On chip regulators

–

Supplies the analog block and the digital core.

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Clock and PLL

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Provides all the clocks required for the video timing.

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Non-volatile memory (NVM)

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Stores production test data and part-to-part variation data for image quality

enhancement.

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Temperature sensors

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Allows the application to take decisions based on the sensor temperature.

3.1

Analog video block

The custom analog block (CAB) includes the following main functional blocks:

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pixel array, see Section 3.1.1

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X, Y address, see Section 3.1.2

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dual column ADCs, see Section 3.1.3

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dual SRAM, see Section 3.1.4

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power management, see Section 3.1.5

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multiple exposure HDR pixel, see Section 3.1.6

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