FXLS8964AF datasheet(41/98 Pages) NXP

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NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

41 / 98

When

SENS_CONFIG2[F_READ] = 1, the MSB of each axis's data will be stored at the

LSB address, regardless of the setting made in

SENS_CONFIG2[LE_BE].

In little-endian mode, the output data registers are arranged with the LSB of each axis's

data stored at the lower address. The upper nibble (MSB) is stored at the next address,

in right justified format. In little-endian mode the MSB is sign extended to form a 16-bit 2's

complement value.

In big-endian mode (

SENS_CONFIG2[LE_BE] = 1), the output data registers are

arranged with the MSB of each axis's data stored at the lower register address. The

lower nibble is stored at the next address, and is left justified. The big-endian option

allows a big-endian processor to directly read the output data into an array without the

need to perform byte swaps. The host software will still have to right shift the data by 4

bits (or divide by 16) in order to obtain the correct scaling of the output data. The sign

extension of the data may need to be done explicitly, depending on the C compiler used.

Notes:

• There will be a ~40 µs delay between the ADC acquisitions of the accelerometer X,Y,Z,

and temperature data. The temperature data is acquired first, followed by the X, Y, and

Z axes acceleration data. All data is latched into the output registers at the same time

instant, coincident with the SRC_DRDY event flag being asserted. Whenever any of

the

OUT_X/Y/Z registers is read the SRC_DRDY event flag is cleared.

• SX means sign extension, which is the logic level of the most significant bit of the 12-bit

OUT_X/Y/Z register data, also known as OUT_X/Y/Z[11].

Table 27. OUT_X_LSB and OUT_X_MSB register (addresses 04h to 05h) with SEN_CONFIG2[LE_BE] = 0 bit

allocation

Bit

Name

OUT_X[7:0]

Reset

—

Access

Bit

Name

OUT_X[11:8]

Reset

—

Access

Table 28. OUT_Y_LSB and OUT_Y_MSB register (addresses 06h to 07h) with SEN_CONFIG2[LE_BE] = 0 bit

allocation

Bit

Name

OUT_Y[7:0]

Reset

—

Access

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