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FXLS8964AF Datenblatt(PDF) 95 Page - NXP Semiconductors

Teilenummer FXLS8964AF
Bauteilbeschribung  3-Axis Low-g Accelerometer
PDF  98 Pages
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Hersteller  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXLS8964AF Datenblatt(HTML) 95 Page - NXP Semiconductors

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NXP Semiconductors
FXLS8964AF
3-Axis Low-g Accelerometer
FXLS8964AF
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Objective data sheet
Rev. 2 — 30 October 2020
95 / 98
Tab. 56. INTx pin behavior as a function of INT_PP_
OD and INT_POL bit settings (valid only
when BT_MODE = VDD) ................................ 56
Tab. 57. INTx pin behavior as a function of INT_PP_
OD and INT_POL bit settings (valid only
when BT_MODE = VDD) ................................ 57
Tab. 58. SENS_CONFIG5 register (address 19h) bit
allocation ......................................................... 57
Tab. 59. SENS_CONFIG5 register (address 19h) bit
description ....................................................... 57
Tab. 60. WAKE_IDLE_LSB register (address 1Ah) bit
allocation ......................................................... 58
Tab. 61. WAKE_IDLE_MSB register (address 1Bh)
bit allocation .................................................... 58
Tab. 62. SLEEP_IDLE_LSB register (address 1Ch)
bit allocation .................................................... 59
Tab. 63. SLEEP_IDLE_MSB register (address 1Dh)
bit allocation .................................................... 59
Tab. 64. ASLP_COUNT_LSB register (address 1Eh)
bit allocation .................................................... 60
Tab. 65. ASLP_COUNT_LSB register (address 1Eh)
bit description .................................................. 60
Tab. 66. ASLP_COUNT_MSB register (address 1Fh)
bit allocation .................................................... 60
Tab. 67. ASLP_COUNT_MSB register (address 1Fh)
bit description .................................................. 60
Tab. 68. ASLP_COUNT timer period ............................ 60
Tab. 69. Auto-WAKE/SLEEP
Interrupt
Event
Sources ........................................................... 61
Tab. 70. INT_EN register (address 20h) bit allocation ... 62
Tab. 71. INT_EN
register
(address
20h)
bit
description ....................................................... 62
Tab. 72. INT_PIN_SEL register (address 21h) bit
allocation ......................................................... 63
Tab. 73. INT_PIN_SEL register (address 21h) bit
description ....................................................... 64
Tab. 74. OFF_X register (addresses 22h) bit
allocation ......................................................... 65
Tab. 75. OFF_Y register (addresses 23h) bit
allocation ......................................................... 65
Tab. 76. OFF_Z register (addresses 24h) bit
allocation ......................................................... 65
Tab. 77. BUF_CONFIG1 register (address 26h) bit
allocation ......................................................... 65
Tab. 78. BUF_CONFIG1 register (address 26h) bit
description ....................................................... 65
Tab. 79. BUF_CONFIG2 register (address 27h) bit
allocation ......................................................... 67
Tab. 80. BUF_CONFIG2 register (address 27h) bit
description ....................................................... 67
Tab. 81. ORIENT_STATUS register (address 28h) bit
allocation ......................................................... 68
Tab. 82. ORIENT_STATUS register (address 28h) bit
description ....................................................... 68
Tab. 83. ORIENT_CONFIG register (address 29h) bit
allocation ......................................................... 69
Tab. 84. ORIENT_CONFIG register (address 29h) bit
description ....................................................... 69
Tab. 85. ORIENT_DBCOUNT register (address 2Ah)
bit allocation .................................................... 70
Tab. 86. ORIENT_DBCOUNT register (address 2Ah)
bit description .................................................. 70
Tab. 87. ORIENT_BF_ZCOMP register (address
2Bh) bit allocation ........................................... 70
Tab. 88. ORIENT_BF_ZCOMP register (address
2Bh) bit description ......................................... 71
Tab. 89. ORIENT_ZLOCK lock-out angles ....................71
Tab. 90. ORIENT Back/Front orientation transition
angle definitions .............................................. 71
Tab. 91. ORIENT_THS register (address 2Ch) bit
allocation ......................................................... 71
Tab. 92. Orientation change trip angles look-up table ....72
Tab. 93. Resultant trip angle (threshold angle ±
hysteresis angle) ............................................. 73
Tab. 94. Orientation change ideal orientation angle
definitions ........................................................ 73
Tab. 95. SDCD_INT_SRC1 register (address 2Dh)
bit allocation .................................................... 74
Tab. 96. SDCD_INT_SRC1 register (address 2Dh)
bit description .................................................. 75
Tab. 97. SDCD_INT_SRC2 register (address 2Eh)
bit allocation .................................................... 76
Tab. 98. SDCD_INT_SRC2 register (address 2Eh)
bit description .................................................. 76
Tab. 99. SDCD_CONFIG1 register (address 2Fh) bit
allocation ......................................................... 77
Tab. 100. SDCD_CONFIG1 register (address 2Fh) bit
description ....................................................... 77
Tab. 101. SDCD_CONFIG2 register (address 30h) bit
allocation ......................................................... 78
Tab. 102. SDCD_CONFIG2 register (address 30h) bit
description ....................................................... 78
Tab. 103. SDCD_OT_DBCNT register (address 31h)
bit allocation .................................................... 80
Tab. 104. SDCD_OT_DBCNT register (address 31h)
bit description .................................................. 80
Tab. 105. SDCD_WT_DBCNT register (address 32h)
bit allocation .................................................... 81
Tab. 106. SDCD_WT_DBCNT register (address 32h)
bit description .................................................. 81
Tab. 107. SDCD_LTHS_LSB register (address 33h)
bit allocation .................................................... 81
Tab. 108. SDCD_LTHS_LSB register (address 33h)
bit description .................................................. 81
Tab. 109. SDCD_LTHS_MSB register (address 34h)
bit allocation .................................................... 82
Tab. 110. SDCD_LTHS_MSB register (address 34h)
bit description .................................................. 82
Tab. 111. SDCD_UTHS_LSB register (address 35h)
bit allocation .................................................... 82
Tab. 112. SDCD_UTHS_LSB register (address 35h)
bit description .................................................. 82
Tab. 113. SDCD_UTHS_MSB register (address 36h)
bit allocation .................................................... 83
Tab. 114. SDCD_UTHS_MSB register (address 36h)
bit description .................................................. 83



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