FXLS8964AF datasheet(63/98 Pages) NXP

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NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

63 / 98

Field

Description

BOOT_DIS

Boot interrupt output disable

0 (default): Boot interrupt is enabled and routed to either the INT1 or INT2 output pin as determined

by the setting made in

INT_PIN_SEL. This interrupt is pulsed, with the polarity of the pulse

determined by the setting made in

SENS_CONFIG4[INT_POL].

1: Interrupt is disabled and not routed to the INTx output pins.

When BT_MODE = GND:

The SRC_BOOT interrupt is signalled on the INTx pin selected in

INT_PIN_SEL and pulsed for a

duration of TPULSE-BOOT1 µs when the BOOT process completes.

When BT_MODE = VDD:

This bit is ignored and the SRC_BOOT interrupt is internally enabled and mapped to the INT2/

BOOT_OUT pin (fixed settings). The INT2/BOOT_OUT pin is pulsed low for a duration of TPULSE-

BOOT2 ms during the BOOT sequence. Note: The BOOT_DIS bit will hold the user programmed value

until the VDD supply is removed or Hibernate mode is entered; this setting is, however, maintained

across a soft reset operation.

WAKE_OUT_EN

WAKE power state output enable

0 (default): The device does not signal the WAKE operating mode on the INTx output pin.

1: The device signals that it is currently in WAKE mode via the INT1 or INT2 pin. Whenever

SYS_

MODE[sys_mode] = 01b, the INT1 or INT2 pin (as selected in INT_PIN_SEL) is held high or low,

depending on the setting made in

SENS_CONFIG4[INT_POL]. The logic state is maintained as long

as the device remains in WAKE mode. When the device leaves WAKE mode and enters SLEEP or

EXT_TRIG mode, the selected interrupt pin assumes the opposite logic state.

Note: If the host system is utilizing the WAKE_OUT function to control an external load switch or LDO

enable signal, other enabled interrupts should not be mapped to the same pin that is assigned to the

WAKE_OUT function in order to prevent unintended operation of the load switch or LDO.

13.22 INT_PIN_SEL register (address 21h)

This register may be used to control the routing of event flags to either the INT1 or INT2

output pins.

Notes:

• When the INT2 pin is configured for the external trigger function, for example, when

SENS_CONFIG4[INT2_FUNC] = 1, a logic '1' value in any of these bit fields is ignored.

• When BT_MODE = VDD, the only interrupt that may be mapped to the INT2/

BOOT_OUT pin is the SRC_BOOT interrupt; setting any of the other bits in this register

to '1' will effectively unroute the respective interrupt source from both the INT1 and

INT2 pins.

Table 72. INT_PIN_SEL register (address 21h) bit allocation

Bit

Name

DRDY_

INT2

BUF_INT2

SDCD_

OT_INT2

SDCD_

WT_INT2

ORIENT_

INT2

ASLP_INT2

BOOT_

INT2

WAKE_

OUT_INT2

Reset

Access

R/W

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