AT25SF641B datasheet(23/59 Pages) DIALOG

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AT25SF641B

DS-AT25SF641B–191D–12-2020

Figure 8-2. Page Program

8.2

Quad Page Program (32h)

This instruction is for programming the memory using pins: IO0, IO1, IO2, and IO3. To use this instruction, the

Quad enable (bit 9 in Status Register) must be set (QE=1). A Write Enable instruction must previously have been

executed to set the Write Enable Latch bit before sending the Page Program instruction. The Quad Page Program

instruction is entered by driving CS low, followed by the command code (32H), three address bytes, and at least

one data byte on I/O pins.

Figure 8-3 shows the instruction sequence. If more than 256 bytes are sent to the device, previously latched data

are discarded, and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If

fewer than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without

affecting other bytes of the same page. CS must be driven high after the eighth bit of the last data byte has been

latched in; otherwise, the Quad Page Program instruction is not executed.

As soon as CS is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is initiated. While

the Quad Page Program cycle is in progress, the Status Register can be read to check the value of the Write in

Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Quad Page Program cycle; it is 0

when done. At some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A Quad

Page Program instruction applied to a page which is protected by the Block Protect (BP4, BP3, BP2, BP1, BP0)

bits (see Table 9-1 and Table 9-2) is not executed.

Figure 8-3. Quad Page Program (32h) Timing

SCK

MSB

00000010

839

37 38

31 32

29 30

OPCODE

HIGH-IMPEDANCE

AAA

MSB

DDDDDDDD

ADDRESS BITS A23-A0

DATA IN BYTE 1

MSB

DDDDDDDD

DATA IN BYTE n

I/O0

(SI)

SCK

37 38

31 32

COMMAND

AAAA

AAA

Address Bits A23-A0

I/O1

(SO)

HIGH-IMPEDANCE

I/O2

(WP)

HIGH-IMPEDANCE

I/O3

(HOLD)

HIGH-IMPEDANCE

DATA

IN 1

DATA

IN 2

DATA

IN 3

DATA

IN 4

DATA

IN 5

D5 D1 D5 D1 D5 D1 D5 D1 D5 D1

D6 D2 D6 D2 D6 D2 D6 D2 D6 D2

MSB

D7 D3 D7 D3 D7 D3 D7 D3 D7 D3

D4 D0 D4 D0 D4 D0 D4 D0 D4 D0

MSB

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