AT25SF641B datasheet(32/59 Pages) DIALOG

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AT25SF641B

DS-AT25SF641B–191D–12-2020

10.

Security Register Commands

The device contains three extra pages, called Security Registers, that can be used for unique device serialization,

system-level Electronic Serial Number (ESN) storage, locked key storage, etc. The Security Registers are

independent of the main Flash memory.

Each page of the Security Register can be erased and programmed independently. Each page can also be

independently locked to prevent further changes.

10.1 Read Unique ID Number (4Bh)

The Read Unique ID Number instruction accesses a factory-set, read-only 64-bit number that is unique to each

AT25SF641B device. The ID number can be used in conjunction with user software methods to help prevent

copying or cloning of a system. The Read Unique ID instruction is initiated by driving the CS pin low and shifting

the instruction code 4Bh, followed by four dummy byte clock cycles. After this, the 64-bit ID is shifted out on the

falling edge of SCLK, as shown in Figure 10-1.

Figure 10-1. Read Unique ID Timing (SPI Mode)

10.2 Erase Security Registers (44h)

Before an erase Security Register Page command can be started, the Write Enable command must have been

previously issued to the device to set the WEL bit of the Status Register to a logical “1” state.

To perform an Erase Security Register Page command, the CS pin must first be asserted and the opcode 44h

must be clocked into the device. After the opcode has been clocked in, the three address bytes specifying the

Security Register Page to be erased must be clocked in. When the CS pin is deasserted, the device erases the

appropriate page. The erasing of the page is internally self-timed and takes place in a time of tPP.

Since the Erase Security Register Page command erases a region of bytes, the lower-order address bits do not

need to be decoded by the device. Thus, address bits A7-A0 are ignored by the device. Despite the lower-order

address bits not being decoded by the device, the complete three address bytes must be clocked into the device

before the CS pin is deasserted, and the CS pin must be deasserted right after the last address bit (A0); otherwise,

the device aborts the operation, and no erase operation is performed.

While the device is executing a successful erase cycle, the Status Register can be read and indicates that the

device is busy. For faster throughput, it is recommended that the Status Register be polled (rather than waiting the

01234567

Mode 0

Mode 3

Instruction

SCLK

4BH

HIGH-IMPEDANCE

Dummy Byte

Mode 0

Mode 3

SCLK

100 101

102

Dummy Byte 3

Dummy Byte 4

64- bit Unique

Serial Number

MSB

103

HIGH-IMPEDANCE

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